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CHAPTER 8
GTL+ INTERFACE SPECIFICATIONS
This section defines the new open-drain bus called GTL+. The primary target audience is
designers developing systems using GTL+ devices such as the Pentium II processor and the
82440FX PCIset. This specification will also be useful for I/O buffer designers developing an
I/O cell and package to be used on a GTL+ bus.
This specification is an enhancement to the GTL (Gunning Transceiver Logic) specification.
The enhancements were made to allow the interconnect of up to eight devices operating at
66.6 MHz and higher using manufacturing techniques that are standard in the microprocessor
industry. The specification enhancements over standard GTL provide better noise margins
and reduced ringing. Since this specification is different from the GTL specification, it is
referred to as GTL+.
The GTL+ specification defines an open-drain bus with external pull-up resistors providing
termination to a termination voltage (V
). The specification includes a maximum driver
TT
output low voltage (V
) value, output driver edge rate requirements, example AC timings,
OL
maximum bus agent loading (capacitance and package stub length), and a receiver threshold
(V
) that is proportional to the termination voltage.
REF
The specification is given in two parts. The first, is the system specification which describes
the system environment. The second, is the actual I/O specification, which describes the AC
and DC characteristics for an I/O transceiver.
Note that some of the critical distances, such as routing length, are given in electrical length
(time) instead of physical length (distance). This is because the system design is dependent
on the propagation time of the signal on a printed circuit board trace rather than just the
length of the trace. Different substrate materials, package materials and system construction
result in different signal propagation velocities. Therefore a given physical length does not
correspond to a fixed electrical length. The length calculation is up to the designer.
8.1.
SYSTEM SPECIFICATION
Figure 8-1 shows a typical system that a GTL+ device would be placed into. The typical
system is shown with two terminations and multiple transceiver agents connected to the bus.
The receivers have differential inputs connected to a reference voltage, V
, which is
REF
generated externally by a voltage divider. Typically, one voltage divider exists at each
component. Here one is shown for the entire network.
8-1
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