Processor Edge Finger Signal Listing - Intel Pentium II Developer's Manual

11.2. PROCESSOR EDGE FINGER SIGNAL LISTING

Table 11-3 is the processor substrate edge finger listing in order by pin number.
Table 11-3. Signal Listing in Order by Pin Number
Pin
No. Pin Name
A1 VCC_VTT
A2 GND
A3 VCC_VTT
A4 IERR#
A5 A20M#
A6 GND
A7 FERR#
A8 IGNNE#
A9 TDI
A10 GND
A11 TDO
A12 PWRGOOD
A13 TESTHI
A14 GND
A15 THERMTRIP#
A16 Reserved
A17 LINT[0]/INTR
A18 GND
A19 PICD[0]
A20 PREQ#
A21 BP#[3]
A22 GND
A23 BPM#[0]
A24 BINIT#
A25 DEP#[0]
S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS
Signal Buffer Type
GTL+ V Supply
TT
V
SS
GTL+ V Supply
TT
CMOS Output
CMOS Input
V
SS
CMOS Output
CMOS Input
JTAG Input
V
SS
JTAG Output
CMOS Input
CMOS Test Input
V
SS
CMOS Output
Reserved for Future Use
CMOS Input
V
SS
CMOS I/O
CMOS Input
GTL+ I/O
V
SS
GTL+ I/O
GTL+ I/O
GTL+ I/O
Pin
No. Pin Name
B1 EMI
B2 FLUSH#
B3 SMI#
B4 INIT#
B5 VCC_VTT
B6 STPCLK#
B7 TCK
B8 SLP#
B9 VCC_VTT
B10 TMS
B11 TRST#
B12 Reserved
B13 VCC_CORE
B14 Reserved
B15 Reserved
B16 LINT[1]/NMI
B17 VCC_CORE
B18 PICCLK
B19 BP#[2]
B20 Reserved
B21 BSEL#
B22 PICD[1]
B23 PRDY#
B24 BPM#[1]
B25 VCC_CORE
Signal Buffer Type
EMI Management
CMOS Input
CMOS Input
CMOS Input
GTL+ V Supply
TT
CMOS Input
JTAG Input
CMOS Input
GTL+ V Supply
TT
JTAG Input
JTAG Input
Reserved for Future Use
Processor Core V
CC
Reserved for Future Use
Reserved for Future Use
CMOS Input
Processor Core V
CC
APIC Clock Input
GTL+ I/O
Reserved for Future Use
GND
CMOS I/O
GTL+ Output
GTL+ I/O
Processor Core V
CC
11-13