Signal Note 7: Tck - Intel Pentium II Developer's Manual

ITP Port
TCK
or TMS
Resistors Located < 1"
from ITP Port
Figure 13-4. TCK/TMS with Daisy Chain Configuration, 2-Way MP Configuration
13.1.4.3.

SIGNAL NOTE 7: TCK

TCK is a high speed signal and should be routed accordingly. Follow the guidelines below to
assure the quality of the signal when beginning use of the ITP to debug the target.
Due to the number of loads on the TCK signal, special care should be taken when routing it.
Poor routing can lead to multiple clocking of some agents on the debug chain, usually on the
falling edge of TCK. This causes information to be lost through the chain and can result in
bad commands being issued to some agents on the bus. Systems using other TCK routing
schemes, particularly those with 'T' or 'Y' configurations where the trace from the source to
the 'T' is long, could have signal integrity problems.
The signal is easily routed as a daisy chain. It is recommended that a pull-up resistor from
TCK to 2.5V be placed at the physically most distant node of the TCK route (see
Figure 13-5).
V
CC_2.5
V
CC_2.5
R 1 kΩ
P
R 47Ω
S
Motherboard Trace
R 47Ω
S
Motherboard Trace
INTEGRATION TOOLS
Slot 1 Connector A
Slot 1 Connector B
13-7