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ELECTRICAL SPECIFICATIONS
7.9.
TEST ACCESS PORT (TAP) CONNECTION
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic,
it is recommended that the Pentium II processor be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to connect to
the rest of the chain unless one of the other components is capable of accepting a 2.5V input.
Similar considerations must be made for TCK, TMS and TRST#. Two copies of each signal
may be required with each driving a different voltage level.
The Debug Port will have to be placed at the start and end of the TAP chain with the TDI of
the first component coming from the Debug Port and the TDO from the last component going
to the Debug Port. In a 2-way MP system, be cautious when including an empty Slot 1
connector in the scan chain. All connectors in the scan chain must have a processor installed
to complete the chain or the system must support a method to bypass empty connectors; the
Slot 1 terminator substrate connects TDI to TDO.
7.10. MAXIMUM RATINGS
Table 7-5 contains Pentium II processor stress ratings only. Functional operation at the
absolute maximum and minimum is not implied nor guaranteed. The processor should not
receive a clock while subjected to these conditions. Functional operating conditions are given
in the AC and DC tables. Extended exposure to the maximum ratings may affect device
reliability. Furthermore, although the processor contains protective circuitry to resist damage
from static electric discharge, one should always take precautions to avoid high static
voltages or electric fields.
7.11. PROCESSOR SYSTEM BUS DC SPECIFICATIONS
The processor DC specifications in this section are defined at the Pentium II processor edge
fingers. See Appendix A for the processor edge finger signal definitions.
Most of the signals on the Pentium II processor system bus are in the GTL+ signal group.
These signals are specified to be terminated to 1.5V. The DC specifications for these signals
are listed in Figure 7-8.
To allow connection with other devices, the Clock, CMOS, APIC and TAP are designed to
interface at non-GTL+ levels. The DC specifications for these pins are listed in Figure 7-8.
Table 7-6 through Table 7-8 list the DC specifications for the Pentium II processor.
Specifications are valid only while meeting specifications for case temperature, clock
frequency and input voltages. Care should be taken to read all notes associated with each
parameter.
7-14
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