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DATA INTEGRITY
•
The PC compatibility signals FERR#, IGNNE#, A20M#, and FLUSH# are not protected.
•
The system support signals SMI# and STPCLK# are not protected.
4.2.4.
Hard-Error Response
The target can assert a hard-error response to a transaction that has generated an error. The
central agent can also claim responsibility for a transaction after response time-out expiration
and terminate the transaction with a hard error response.
On observing a hard-error response, the initiator may treat it as a unrecoverable or a fatal
error.
4.2.5.
Pentium
4.2.5.1.
PARITY ALGORITHM
All bus parity signals use the same algorithm to compute correct parity. A correct parity
signal is high if all covered signals are high, or if an even number of covered signals are low.
A correct parity signal is low if an odd number of covered signals are low. Parity is computed
using voltage levels, regardless of whether the covered signals are active-high or active-low.
Depending on the number of covered signals, a parity signal can be viewed as providing
"even" or "odd" parity; this specification does not use either term.
4.2.5.2.
PENTIUM
The Pentium II processor system bus uses an ECC code that can correct single-bit errors,
detect double-bit errors, and detect all errors confined to one nibble (SEC-DED-S4ED).
System designers may choose to detect all these errors, or a subset of these errors. They may
also choose to use the same ECC code in L3 caches, main memory arrays, or I/O subsystem
buffers.
4-4
®
II Processor System Bus Error Code Algorithms
®
II SYSTEM BUS ECC ALGORITHM
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