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SIGNALS REFERENCE
A 16-byte transfer on a 64-bit data bus with a 32-byte cache line size is a part-line transfer,
where a chunk is eight bytes aligned on an eight-byte boundary. All chunks in the span of a
part-line transfer are moved across the data bus. Address bits A[4:3]# determines the transfer
order for the included chunks, using the burst order specified in Table A-3 for line transfers.
A.1.15.3.
PARTIAL TRANSFERS
On a 64-bit data bus, a partial transfer moves from 0-8 bytes within an aligned 8-byte span to
or from a memory or I/O address.
Processors convert non-cacheable misaligned memory accesses that cross 8-byte boundaries
into two partial transfers. For example, a non-cacheable, misaligned 8-byte read requires two
Read Data Partial transactions. Similarly, processors convert I/O write accesses that cross 4-
byte boundaries into 2 partial transfers. I/O reads are treated the same as memory reads.
I/O Read and I/O Write transactions are 1 to 4 byte partial transactions.
A.1.16. DBSY# (I/O)
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on
the Pentium II processor system bus to indicate that the data bus is in use. The data bus is
released after DBSY# is deasserted. This signal must connect the appropriate pins on all
Pentium II processor system bus agents.
A.1.17. DEFER# (I)
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the
addressed memory or I/O agent. This signal must connect the appropriate pins of all Pentium
II processor system bus agents.
A.1.18. DEP[7:0]# (I/O)
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection for the
data bus. They are driven by the agent responsible for driving D[63:0]#, and must connect the
appropriate pins of all Pentium II processor system bus agents which use them. The
DEP[7:0]# signals are enabled or disabled for ECC protection during power on configuration.
A.1.19. DRDY# (I/O)
The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-cycle data transfer, DRDY# may be
A-6
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