Related Manuals for Intel DUAL-CORE - SPECIFICATION UPDATE REV 010
Summary of Contents for Intel DUAL-CORE - SPECIFICATION UPDATE REV 010
- Page 1 Intel® Pentium® Dual-Core Processor Specification Update December 2010 Revision 010...
- Page 2 DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
-
Page 3: Table Of Contents
Contents Preface ..........................5 Summary Tables of Changes ....................7 Identification Information ....................15 Errata ..........................17 Specification Changes ......................55 Specification Clarifications ....................56 Documentation Changes ...................... 57 Specification Update... - Page 4 August 2007 Family • Added M-0 stepping errata 316515 -006 • Added Processors based on the Intel Mobile 965 series September 2007 chipset. • Added M-0 Errata and Microcode in separate tables • Removed Errata AN11, AN19, AN21, AN42, AN55, AN63, AN 69, AN72, AN74, AN79, AN83, AN96, AN104, AN5S and AN11S.
-
Page 5: Preface
318125 Family Datasheet Related Documents Document Title Document Number/Location Debug Port Design Guide for Crestline and Intel® 945PM/GM/GT and Note 940GML Express Chipset Systems Intel® 64 and IA-32 Architectures Software Developer's Manual, 253665 Volume 1: Basic Architecture Intel® 64 and IA-32 Architectures Software Developer's Manual,... - Page 6 Preface Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number Errata are design defects or errors.
-
Page 7: Summary Tables Of Changes
The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed Processor steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted. - Page 8 V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA Package W= Intel® Celeron®-M processor X = Intel® Pentium® M processor on 90-nm process with 2-MB L2 cache and Intel® Processors A100 and A110 with 512-kB L2 cache Y = Intel®...
- Page 9 AT = Intel® Celeron® processor 200 series AU = Mobile Value Celeron AV = Intel® Core™2 Extreme Processor QX9000 Sequence and Intel® Core™2 Quad Processor Q9000 Sequence processor AX = Quad-Core Intel® Xeon® Processor 5400 Series AY = Wolfdale DP Note: Δ...
- Page 10 Summary Tables of Changes Number Plans ERRATA AN12 Fixed FP Inexact-Result Exception Flag May Not Be Set A Locked Data Access that Spans Across Two Pages May Cause the AN13 Fixed System to Hang AN14 No Fix MOV To/From Debug Registers Causes Debug Exception AN15 No Fix INIT Does Not Clear Global Entries in the TLB...
- Page 11 Summary Tables of Changes Number Plans ERRATA Programming the Digital Thermal Sensor (DTS) Threshold May AN35 No Fix Cause Unexpected Thermal Interrupts AN36 Erratum removed AN37 No Fix The Processor May Report a #TS Instead of a #GP Fault AN38 Fixed BTS Message May be Lost when the STPCLK# Signal is Active Certain Performance Monitoring Counters Related to Bus, L2 Cache...
- Page 12 Summary Tables of Changes Number Plans ERRATA MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum AN58 No Fix Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data after a Machine Check Exception (MCE) Using Memory Type Aliasing with Memory Types WB/WT May Lead AN59 Fixed to Unpredictable Behavior...
- Page 13 Summary Tables of Changes Number Plans ERRATA Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not AN81 No Fix Count Some Transitions AN82 No Fix Count Value for Performance-Monitoring Counter PMH_PAGE_WALK May Be Incorrect AN83 No Fix Erratum Removed AN84 No Fix Some Bus Performance Monitoring Events May Not Count Local Events under Certain Conditions AN85 No Fix...
- Page 14 Summary Tables of Changes Number Plans ERRATA AN105 No Fix BIST Failure after Reset Instruction Fetch May Cause a Livelock during Snoops of the L1 AN106 No Fix Data Cache Use of Memory Aliasing with Inconsistent Memory Type May Cause a AN107 No Fix System Hang or a Machine Check Exception...
-
Page 15: Identification Information
Identification Information Identification Information Component Marking Information Figure 1. Intel® Pentium® Dual-Core Mobile Processor on 65-nm Process (Micro- FCPGA/FCBGA) S-Spec Markings Table 1. Pentium Dual-Core Mobile Processor on 65-nm Process Identification Information QDF/S- Processor # Package Stepping CPUID FSB(MHz) Speed... - Page 16 Identification Information Table 2. Pentium Dual-Core Mobile Processor on 65-nm Process Identification Information for 965 Express Chipset Family QDF/S- Processor # Package Stepping CPUID FSB(MHz) Speed Notes SPEC# HFM/LFM (GHz) SLAEC T2310 Micro-FCPGA 06FDh 1.46/800 SLA4J T2370 Micro-FCPGA 06FDh 1.73/800 SLA4K T2330 Micro-FCPGA...
-
Page 17: Errata
Null segment. If the numeric exception handler tries to access the FST data it will get a #GP fault. Intel has not observed this erratum with any commercially available software, or system. - Page 18 Incorrect Data Size or Lead to Memory-Ordering Violations Problem: Under certain conditions as described in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide, the processor performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP...
- Page 19 Implication: When this erratum occurs, the values for FPUDataPointer in the saved floating point image structure may appear to be random values. Executing any non-control FP instruction with memory operand will initialize the FPUDataPointer. Intel has not observed this erratum with any commercially available software.
- Page 20 Invalid entries in the Page-Directory-Pointer-Table Register (PDPTR) that have the reserved bits set to one may cause a General Protection (#GP) exception. Implication: Intel has not observed this erratum with any commercially available software. Workaround: Do not set the reserved bits to one when PDPTR entries are invalid.
- Page 21 Errata AN12. FP Inexact-Result Exception Flag May Not Be Set Problem: When the result of a floating-point operation is not exactly represented in the destination format (1/3 in binary form, for example), an inexact-result (precision) exception occurs. When this occurs, the PE bit (bit 5 of the FPU status word) is normally set by the processor.
- Page 22 An instruction with lock data access that spans across two pages may, given Problem: some rare internal conditions, hang the system. Implication: When this erratum occurs, the system may hang. Intel has not observed this erratum with any commercially available software or system. Workaround: A locked data access should always be aligned.
- Page 23 Workaround: Although it is possible to have a single physical page mapped by two different linear addresses with different memory types, Intel has strongly discouraged this practice as it may lead to undefined results. Software that needs to implement memory aliasing should manage the memory type consistency.
- Page 24 Locked transaction is pipelined on the front side bus (FSB), LOCK# may unexpectedly deassert. Implication: When this erratum occurs, the system may hang during shutdown. Intel has not observed this erratum with any commercially available systems or software.
- Page 25 Errata AN24. Disabling of Single-step on Branch Operation May Be Delayed following a POPFD Instruction Problem: Disabling of Single-step On Branch Operation may be delayed, if the following conditions are met: “Single Step On Branch Mode” is enabled (DebugCtlMSR.BTF and EFLAGS.TF are set) POPFD used to clear EFLAGS.TF A jump instruction (JMP, Jcc, etc.) is executed immediately after POPFD Implication: Single-step On Branch mode may remain in effect for one instruction after the POPFD...
- Page 26 Errata AN26. VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (LER) MSR Problem: The LER MSR may be unexpectedly updated, if the resultant value of the Zero Flag (ZF) is zero after executing the following instructions: VERR (ZF=0 indicates unsuccessful segment read verification) VERW (ZF=0 indicates unsuccessful segment write verification) LAR (ZF=0 indicates unsuccessful access rights load) LSL (ZF=0 indicates unsuccessful segment limit load)
- Page 27 Errata AN29. DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store Instruction May Incorrectly Increment Performance Monitoring Count for Saturating SIMD Instructions Retired (Event CFh) Problem: Performance monitoring for Event CFH normally increments on saturating SIMD instruction retired. Regardless of DR7 programming, if the linear address of a retiring memory store MOVD/MOVQ/MOVNTQ instruction executed matches the address in DR3, the CFH counter may be incorrectly incremented.
- Page 28 Errata AN31. Data Breakpoint/Single Step on MOV SS/POP SS May Be Lost after Entry into SMM Problem: Data Breakpoint/Single Step exceptions are normally blocked for one instruction following MOV SS/POP SS instructions. Immediately after executing these instructions, if the processor enters SMM (System Management Mode), upon RSM (resume from SMM) operation, normal processing of Data Breakpoint/Single Step exceptions is restored.
- Page 29 #GP fault (general protection exception). Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
- Page 30 Errata AN38. BTS Message May Be Lost When the STPCLK# Signal Is Active Problem: STPCLK# is asserted to enable the processor to enter a low-power state. Under some circumstances, when STPCLK# becomes active, a pending BTS (Branch Trace Store) message may be either lost and not written or written with corrupted branch address to the Debug Store area.
- Page 31 • A REP I/O read • An I/O read that redirects to MWAIT. • In systems supporting Intel® Virtualization Technology a fault in the middle of an IO operation that causes a VM Exit Implication: SMM handlers may get false IO_SMI indication.
- Page 32 Errata AN46. SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null Segment Selector” to SS and CS Registers Problem: According to the processor specification, attempting to load a Null segment selector into the CS and SS segment registers should generate a General Protection Fault (#GP).
- Page 33 Errata AN48. Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations Problem: An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero) to emulates real-address mode address wraparound at 1 megabyte. However, if all of the following conditions are met, address bit 20 may not be masked.
- Page 34 Errata AN50. Premature Execution of a Load Operation Prior to Exception Handler Invocation Problem: If any of the below circumstances occur it is possible that the load portion of the instruction will have executed before the exception handler is entered. 1.
- Page 35 Updating a page table entry by changing R/W, U/S or P bits without TLB shootdown (as defined by the 4 step procedure in Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide), in conjunction with a complex sequence of internal processor micro-architectural events, may lead to unexpected processor behavior.
- Page 36 Exposure to this problem requires the use of a data write which spans a cache line boundary. Implication: This erratum may cause loads to be observed out of order. Intel has not observed this erratum with any commercially available software or system.
- Page 37 Implication: Software that uses aliasing of WB and WT memory types may observe unpredictable behavior. Intel chipset-based platforms are not affected by this erratum. Workaround: None identified. Intel does not support the use of WB and WT page memory type aliasing.
- Page 38 Implication: If SMM software changes the values of the EFLAGS.VM in SMRAM, it may result in unpredictable system behavior. Intel has not observed this behavior in commercially available software. Workaround: SMM software should not change the value of EFLAGS.VM in SMRAM.
- Page 39 Errata AN65. A Thermal Interrupt Is Not Generated When the Current Temperature Is Invalid Problem: When the DTS (Digital Thermal Sensor) crosses one of its programmed thresholds it generates an interrupt and logs the event (IA32_THERM_STATUS MSR (019Ch) bits [9,7]). Due to this erratum, if the DTS reaches an invalid temperature (as indicated IA32_THERM_STATUS MSR bit[31]) it does not generate an interrupt even if one of the programmed thresholds is crossed and the corresponding log bits become set.
- Page 40 Architecture, for information on the usage of ENTER instructions. This erratum is not expected to occur in ring 3. Faults are usually processed in ring 0 and stack switch occurs when transferring to ring 0. Intel has not observed this erratum on any commercially-available software.
- Page 41 A or D bits being set in a Page table Entry (PTE)) Implication: Stale Translations may remain valid in TLB after a PTE update resulting in unpredictable system behavior. Intel has not observed this erratum with any commercially available software.
- Page 42 Store Ordering May Be Incorrect between WC and WP Memory Types Problem: According to Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide, WP (Write Protected) stores should drain the WC (Write Combining) buffers in the same way as UC (Uncacheable) memory type stores do.
- Page 43 Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.
- Page 44 Errata AN84. Some Bus Performance Monitoring Events May Not Count Local Events under Certain Conditions Problem: Many Performance Monitoring Events require core-specificity, which specifies which core’s events are to be counted (local core, other core, or both cores). Due to this erratum, some Bus Performance Monitoring events may not count when the core- specificity is set to the local core.
- Page 45 Interrupt or Exception (for example NMI (Non-Maskable Interrupt), Debug break (#DB), Machine Check (#MC), etc.) Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commercially available software. Workaround: None Identified.
- Page 46 Errata AN90. IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET instruction even though alignment checks were disabled at the start of the IRET. This can only occur if the IRET instruction is returning from CPL3 code to CPL3 code.
- Page 47 Errata AN93. B0-B3 Bits in DR6 May Not Be Properly Cleared after Code Breakpoint Problem: B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may not be properly cleared when the following sequence happens: 1. POP instruction to SS (Stack Segment) selector. 2.
- Page 48 Errata AN96. Erratum removed AN97. Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL Is Counted Incorrectly for PMULUDQ Instruction Problem: Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL (Event select 0B3H, Umask 01H) counts the number of SIMD packed multiply micro-ops executed. The count for PMULUDQ micro-ops might be lower than expected. No other instruction is affected.
- Page 49 Errata AN99. Updating Code Page Directory Attributes without TLB Invalidation May Result in Improper Handling of Code #PF Problem: Code #PF (Page Fault exception) is normally handled in lower priority order relative to both code #DB (Debug Exception) and code Segment Limit Violation #GP (General Protection Fault).
- Page 50 As an example, an access to a memory mapped I/O device may be incorrectly marked as cacheable, become cached, and never make it to the I/O device. Intel has not observed this erratum with any commercially available software.
- Page 51 A livelock may be observed in rare conditions when instruction fetch causes multiple level one data cache snoops. Implication: Due to this erratum, a livelock may occur. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for BIOS to contain a workaround for this erratum.
- Page 52 Problem: Under certain conditions, as described in the Software Developers Manual section "Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors", the processor may perform REP MOVS or REP STOS as write combining stores (referred to as “fast strings”) for optimal performance. FXSAVE may also be internally implemented using write combining stores.
- Page 53 WC memory operations. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Intel does not support the use of cacheable and WC memory type aliasing, and WC operations are defined as weakly ordered.
- Page 54 Errata AN112 A 64-bit Register IP-relative Instruction May Return Unexpected Results Problem: Under an unlikely and complex sequence of conditions in 64-bit mode, a register IP- relative instruction result may be incorrect Implication: A register IP-relative instruction result may be incorrect and could cause software to read from or write to an incorrect memory location.
-
Page 55: Specification Changes
Specification Changes Specification Changes There are no specification changes in this specification update revision. § Specification Update... -
Page 56: Specification Clarifications
Specification Clarifications Specification Clarifications There are no specification clarifications in this specification update revision. § Specification Update... -
Page 57: Documentation Changes
Documentation Changes Documentation Changes There are no documentation changes in this specification update revision. Documentation changes for the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volumes 1, 2A, 2B, 3A and 3B will be posted in a separate document, Intel®...