Debug Port Pinout Description And Requirements 1 - Intel Pentium II Developer's Manual

INTEGRATION TOOLS
Table 13-1. Debug Port Pinout Description and Requirements
Name Pin
RESET# 1 Reset signal from MP
cluster to ITP.
DBRESET# 3 Allows ITP to reset entire
target system.
TCK 5 TAP (Test Access Port)
clock from ITP to Slot 1
connectors.
TMS 7 Test mode select signal
from ITP to Slot 1
connectors, controls the
TAP finite state machine
TDI 8 Test data input signal from
ITP to first component in
boundary scan chain of
MP cluster; inputs test
instructions and data
serially.
POWERON 9 Used by ITP to determine
when target system power
is ON and, once target
system is ON, enables all
debug port electrical
interface activity. From
target V
13-4
Description Specification Requirement
•
Terminate
the debug port
•
Debug port must be at the end
of the
•
Tie signal to target system
reset (recommendation: PWR
OK signal on PCIset as an
ORed input)
•
Pulled-up signal with the
proper resistor (see notes)
•
Daisy chain signal to the
processor(s)
Add ~150 Ω pull-up resistor to
•
Vcc 2.5
•
Place pull-up resistor (to
Vcc
2.5
from the debug port.
•
Daisy chain signal to the
processor(s)
Add ~150 Ω pull-up resistor to
•
Vcc 2.5
•
Place pull-up resistor (to
Vcc
2.5
from the debug port.
•
Add ~150 to 330 ohm pull-up
resistor (to Vcc2.5)
•
Add 1K ohm pull-up resistor
(to V
TT
to ITP.
TT
2 signal properly at Connected to high speed
comparator (biased at 2/3 of the
level found at the POWERON
pin) on the ITP buffer board.
signal trace
Additional load does not change
timing calculations for the
processor bus agents if routed
properly.
Open drain output from ITP to
the target system. It will be held
asserted for 100 ms;
capacitance needs to be small
enough to recognize assert. A
240-ohm pull-up resistor is
recommended; signal should be
fine tuned to (1) meet V
target system and (2) meet
specified rise time.
Poor routing can cause multiple
3 clocking problems, usually on
falling edge of TCK. Should be
routed to all components in the
boundary scan chain
way MP systems, each
processor should receive a
) at the point furthest
separately buffered TCK signal.
Operates synchronously with
3 TCK. Should be routed to all
components in the boundary
scan chain
systems, each processor should
receive a separately buffered
TMS signal.
) at the point furthest
Operates synchronously with
TCK.
If no power is applied, the ITP
) will not drive any signals;
isolation provided using isolation
gates. Voltage applied is
internally used to set GTL+
threshold (or reference) at 2/3
V
TT
1
Notes
of
OL
3
. For two-
3
. For two-way MP
.