Table of Contents
Advertisement
SYSTEM BUS OVERVIEW
AERR#, can be enabled or disabled as part of the power on configuration (see Chapter 5,
Configuration). If AERR# is disabled for all system bus agents, request and address parity
errors are ignored and no action is taken by bus agents. If AERR# is enabled for at least one
bus agent, the agents observing the start of a transaction check the Address Parity signals
(AP[1:0]#) and the RP# parity signal and assert AERR# appropriately if an address parity
error is detected.
P6 family processors support two modes of response when the AERR# signal is enabled. This
may be configured at power-up with "AERR# observation" mode. AERR# observation
configuration must be consistent between all bus agents. If AERR# observation is disabled,
AERR# is ignored and no action is taken by the bus agents. If AERR# observation is enabled
and AERR# is sampled asserted, the transaction is canceled. In addition, the requesting agent
may retry the transaction at a later time up to its retry limit, after which the error becomes a
hard error as determined by the initiating processor.
If a transaction is canceled by AERR# assertion, then the transaction is aborted. Snoop
results are ignored if they cannot be canceled in time. All agents reset their rotating ID for
bus arbitration to the state at reset (such that bus agent 0 has highest priority).
BINIT# is used to signal any bus condition that prevents reliable future operation of the bus.
Like the AERR# pin, the BINIT# driver can be enabled or disabled as part of the power-on
configuration (see Chapter 5, Configuration). If the BINIT# driver is disabled, BINIT# is
never asserted and no action is taken on bus errors.
Regardless of whether the BINIT# driver is enabled, the Pentium II processor supports two
modes of operation that may be configured at power on. These are the BINIT# observation
and driving modes. If BINIT# observation is disabled, BINIT# is ignored and no action is
taken by the processor even if BINIT# is sampled asserted. If BINIT# observation is enabled
and BINIT# is sampled asserted, all bus state machines are reset. All agents reset their
rotating ID for bus arbitration, and internal state information is lost. L1 and L2 cache
contents are not affected.
The BERR# pin is used to signal any error condition caused by a bus transaction that will not
impact the reliable operation of the bus protocol (for example, memory data error, non-
modified snoop error). A bus error that causes the assertion of BERR# can be detected by the
processor, or by another bus agent. The BERR# driver can be enabled or disabled at power-
on reset. If the BERR# driver is disabled, BERR# is never asserted. If the BERR# driver is
enabled, the processor may assert BERR#.
A machine check exception may or may not be taken for each assertion of BERR# as
configured at power on. A processor will always disable the machine check exception by
default.
If a processor detects an internal error unrelated to bus operation, it asserts IERR#. For
example, a parity error in an L1 or L2 cache causes a Pentium Pro processor to assert IERR#.
A machine check exception may be taken instead of assertion of IERR# as configured with
software.
Two processor agents in the P6 family may be configured as an FRC (functional redundancy
checking) pair. In this configuration, one processor acts as the master and the other acts as a
3-8
Advertisement
Table of Contents
