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Pentium ® II Processor Integration Tool Mechanical Keep Out Volume-
13-13.
Side View .........................................................................................................13-15
A-1.
PWRGOOD Relationship at Power-On............................................................... A-11
Table
Pentium ® II Processor Execution Unit Pipelines..................................................2-13
2-1.
3-1.
Execution Control Signals .................................................................................... 3-2
3-2.
Arbitration Signals................................................................................................ 3-4
3-3.
Request Signals .................................................................................................. 3-5
3-4.
Snoop Signals ..................................................................................................... 3-5
3-5.
Response Signals................................................................................................ 3-6
3-6.
Data Phase Signals ............................................................................................. 3-7
3-7.
Error Signals........................................................................................................ 3-7
3-8.
PC Compatibility Signals...................................................................................... 3-9
3-9.
Diagnostic Support Signals .................................................................................3-10
4-1.
Direct Bus Signal Protection................................................................................. 4-2
APIC Cluster ID Configuration for the Pentium ® II Processor Family 1 ................. 5-5
5-1.
Pentium ® II Processor Bus BREQ[1:0]# Interconnect (Two Agents)..................... 5-5
5-2.
Arbitration ID Configuration with Processors Supporting BR[1:0]# 1 ..................... 5-6
5-3.
Pentium ® II Processor Family Power-On Configuration Register.......................... 5-7
5-4.
Pentium ® II Processor Family Power-On Configuration Register APIC
5-5.
Cluster ID Bit Field............................................................................................... 5-8
Pentium ® II Processor Family Power-On Configuration Register Arbitration
5-6.
ID Configuration................................................................................................... 5-8
Pentium ® II Processor Family Power-On Configuration Register Bus Frequency
5-7.
to Core Frequency Ratio Bit Field ........................................................................ 5-8
6-1.
1149.1 Instructions in the Processor TAP............................................................. 6-7
6-2.
TAP Data Registers ............................................................................................. 6-8
6-3.
Device ID Register............................................................................................... 6-9
6-4.
TAP Reset Actions............................................................................................... 6-9
7-1.
Core Frequency to System Bus Multiplier Configuration ....................................... 7-7
Voltage Identification Definition (1, 2, 3) ..............................................................7-10
7-2.
7-3.
Recommended Pull-Up Resistor Values (Approximate) for CMOS
Signals ...............................................................................................................7-11
Pentium ® II Processor/Slot 1 System Bus Signal Groups....................................7-13
7-4.
Pentium ® II Processor Absolute Maximum Ratings.............................................7-15
7-5.
Pentium ® II Processor/Slot 1 Connector Voltage/Current Specifications..............7-16
7-6.
7-7.
GTL+ Signal Groups DC Specifications...............................................................7-18
7-8.
Non-GTL+ Signal Groups DC Specifications .......................................................7-18
System Bus AC Specifications (Clock) (1, 2) .......................................................7-20
7-9.
Valid Pentium ® II Processor System Bus, Core Frequency and Cache Bus
7-10.
Frequencies (1, 2) ..............................................................................................7-21
Pentium ® II Processor System Bus AC Specifications (GTL+ Signal Group) .......7-21
7-11.
Pentium ® II Processor System Bus AC Specifications (CMOS Signal Group)......7-22
7-12.
7-13.
System Bus AC Specifications (Reset Conditions)...............................................7-22
System Bus AC Specifications (APIC Clock and APIC I/O) (1, 2) .........................7-23
7-14.
System Bus AC Specifications (TAP Connection) (1) ..........................................7-24
7-15.
Pentium ® II Processor GTL+ Bus Specifications (1) ............................................. 8-3
8-1.
8-2.
Specifications for Signal Quality ........................................................................... 8-4
8-3.
I/O Buffer DC Parameters...................................................................................8-13
Tables
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