Software-Programmable Options - Intel Pentium II Developer's Manual

and IGNNE# on the inactive-to-active transition of RESET# to determine the core-frequency
to bus-frequency relationship and immediately begins the internal PLL lock mode. On the
active-to-inactive transition of RESET#, the processor internally latches the inputs to allow
the pins to be used for normal functionality. Effectively, these pins must meet a large setup
time (1 ms) to the active-to-inactive transition of RESET#.
Table 7-1 describes the relationship between bus frequency and core frequency.
5.3.

SOFTWARE-PROGRAMMABLE OPTIONS

All bus agents are required to maintain some software read/writeable bits in the power-on
configuration register for software-configured options. This register inside P6 family
processors is defined in Table 5-4.
Table 5-4. Pentium
Feature
Output tristate enabled
Execute BIST
Data error checking enabled
Response error checking enabled
FRCERR observation enabled
AERR# driver enabled
AERR# observation enabled
BERR# driver enabled for initiator bus
requests
BERR# driver enabled for target bus
requests
BERR# driver enabled for initiator
internal errors
BERR# observation enabled
BINIT# driver enabled
BINIT# observation enabled
In-order queue depth of 1
1 Mbyte power-on reset vector
FRC Mode enabled
APIC cluster ID
Reserved
Symmetric arbitration ID
® II Processor Family Power-On Configuration Register
Processor
Active Signals
FLUSH#
INIT#
N/A
N/A
N/A
A8#
N/A
N/A
N/A
A9#
N/A
A10#
A7#
A6#
A5#
A12#, A11#
A14#, A13#
BR0#, BR1#,
BR2#, BR3#,
A5#
Processor
Register
Bits Read/Write
D8=1 Read
D9=1 Read
D1=1 Read/Write
D2=1 Read/Write
D3=1 Read/Write
D10=1 Read
D4=1 Read/Write
Reserved Read/Write
D6=1 Read/Write
Reserved Read
D7=1 Read/Write
D12=1 Read
D13=1 Read
D14=1 Read
D15=1 Read
D17, D16 Read
see Table 5-5
D19, D18 —
D21,D20 Read
see Table 5-6
CONFIGURATION
Default
N/A
N/A
Disabled
Disabled
Disabled
N/A
Disabled
Disabled
Disabled
N/A
Disabled
N/A
N/A
N/A
N/A
N/A
—
N/A
5-7