Caches - Intel Pentium II Developer's Manual

Table 2-1. Pentium
Port Execution Unit
0 Integer ALU Unit
0 LEA instructions
0 Shift Instructions
0 Integer Multiplication instruction Latency 4, Throughput 1/cycle
0 Floating-Point Unit
0 FADD instruction
FMUL
FDIV Unit
0 MMX™ Technology ALU Unit
0 MMX Technology Multiplier
Unit
1 Integer ALU Unit
1 MMX Technology ALU Unit
1 MMX Technology Shifter Unit
2 Load Unit
3 Store Address Unit
4 Store Data Unit
NOTES:
1. The FMUL unit cannot accept a second FMUL within the cycle after it has accepted the first. This is NOT
the same as only being able to do FMULs on even clock cycles.
2. FMUL is pipelined one every two clock cycles. One way of thinking about this is to imagine that a P6-
family processor has only a 32x32->32 multiply pipelined.
3. Store latency is not all that important from a dataflow perspective. The latency that matters is with respect
to determining when they can retire and be completed. They also have a different latency with respect to
load forwarding. For example, if the store address and store data of a particular address, for example
100, dispatch in clock cycle 10, a load (of the same size and shape) to the same address 100 can
dispatch in the same clock cycle 10 and not be stalled.
4. A load and store to the same address can dispatch in the same clock cycle.
2.3.2.

Caches

The on-chip cache subsystem of processors with MMX technology consists of two 16K four-
way set associative caches with a cache line length of 32 bytes. The caches employ a write-
MICRO-ARCHITECTURE OVERVIEW
® II Processor Execution Unit Pipelines
Latency/Throughput
Latency 1, Throughput 1/cycle
Latency 1, Throughput 1/cycle
Latency 1, Throughput 1/cycle
Latency 3, Throughput 1/cycle
Latency 5, Throughput 1-2/cycle
Latency long and data dependant, Throughput
non-pipelined
Latency 1, Throughput 1/cycle
Latency 3, Throughput 1/cycle
Latency 1, Throughput 1/cycle
Latency 1, Throughput 1/cycle
Latency 1, Throughput 1/cycle
Latency 3 on a cache hit, Throughput 1/cycle
Latency 3 (N/A)
Throughput 1/cycle (3)
Latency 1 (N/A)
Throughput 1/cycle
Notes
1,2
(3)
4
3
2-13