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The VID pins should be pulled up to a TTL-compatible level with external resistors to the
power source of the regulator only if required by the regulator or external logic monitoring
the VID[4:0] signals. The power source chosen must be guaranteed to be stable whenever the
supply to the voltage regulator is stable. This will prevent the possibility of the processor
supply going above Vcc
case of a DC-to-DC converter, this can be accomplished by using the input voltage to the
converter for the VID line pull-ups. A resistor of greater than or equal to 10K ohms may be
used to connect the VID signals to the converter input. See the Pentium
Distribution Guidelines (Order Number 243332) for further information on power supply
specifications for the Pentium II processor and future Slot 1 processors.
7.7.
PENTIUM
All RESERVED pins must remain unconnected. Connection of Reserved pins to Vcc
Vcc
, V
or to any signal can result in component malfunction or incompatibility with
L2
SS
future Slot 1 products. See Section 5.2. for a pin listing of the processor and the location of
each Reserved pin.
All TESTHI pins must be connected to 2.5V via pull-up resistors of between 1 and 10 KΩ
value.
PICCLK must be driven with a valid clock input and the PICD[1:0] lines must be pulled-up
to 2.5V even when the local APIC will not be used. A separate pull-up resistor must be
provided for each PICD line (see Table 7-3 for recommended values).
Table 7-3. Recommended Pull-Up Resistor Values (Approximate)
Recommended Resistor
Value (Approximate)
150
150–220
150–330
410
500
NOTES:
1.
These resistor values are recommended for system implementations using open drain CMOS buffers.
2.
These approximate resistor values are for proper operation of debug tools only A ~150Ω pull-up resistor
is expected for these signals.
3.
The TRST# signal must be driven low at power on reset. This can be accomplished with a ~680Ω pull-
down resistor.
For pullup resistor values on debug port signals, see Chapter 13, Integration Tools.
4.
in the event of a failure in the supply for the VID lines. In the
CORE
®
II PROCESSOR SYSTEM BUS UNUSED PINS
for CMOS Signals
PICD[0], PICD[1]
FERR#, IERR#, THERMTRIP#
A20M#, IGNNE#, INIT#, LINT[1]/NMI, LINT[0]/INTR, PWRGOOD, SLP#
STPCLK#, SMI#
FLUSH#
ELECTRICAL SPECIFICATIONS
®
II Processor Power
(1, 2, 3, 4)
CMOS Signal
,
CORE
7-11
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