Arbitration Signals - Intel Pentium II Developer's Manual

SYSTEM BUS OVERVIEW
The INIT# input signal resets all processors without affecting their internal (L1 or L2)
caches, floating-point registers, or their Machine Check Architecture registers (MCi–CTL).
Each processor begins execution at the address vector as defined during power on
configuration. INIT# has another meaning on RESET#'s active to inactive transition: if
INIT# is sampled active on RESET#'s active to inactive transition, then the processor
executes its built-in self test (BIST).
If the FLUSH# input signal is asserted, the processor writes back all internal cache lines in
the Modified state (L1 and L2 caches) and invalidates all internal cache lines (L1 and L2
caches). The flush operation puts all internal cache lines in the Invalid state. All lines are
written back and invalidated. The FLUSH# signal has a different meaning when it is sampled
asserted on the active to inactive transition of RESET#. If FLUSH# is sampled asserted on
the active to inactive transition of RESET#, then the processor tristates all of its outputs. This
function is used during board testing.
The Pentium II processor supplies a STPCLK# pin to enable the processor to enter a low
power state. When STPCLK# is asserted, the processor puts itself into the Stop-Grant state.
The processor continues to snoop bus transactions while in Stop-Grant state. When
STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock.
The SLP# signal is the Sleep signal. When asserted in Stop-Grant state, the processor enters a
new low power state, the Sleep state. During Sleep state, the processor stops providing
internal clock signals to all units, only leaves PLL still running. Snooping during the Sleep
state is not supported.
The PICCLK and PICD[1:0]# signals support the Advanced Programmable Interrupt
Controller (APIC) interface. The PICCLK signal is a clock input for the processor's APIC
bus clock. The PICD[1:0]# signals are used for bi-directional serial message passing on the
APIC bus.
LINT[1:0] are local interrupt signals, also defined by the APIC interface. In APIC disabled
mode, LINT0 defaults to INTR, a maskable interrupt request signal. LINT1 defaults to NMI,
a non-maskable interrupt. Both signals are asynchronous inputs. In the APIC enable mode,
LINT0 and LINT1 are defined with the local vector table.
LINT[1:0] are also used along with the A20M# and IGNNE# signals to determine the
multiplier for the internal clock frequency as described in Chapter 5, Configuration.
3.2.2.

Arbitration Signals

The arbitration signal group (see Table 3-2) is used to arbitrate for the bus.
The Pentium II processor permits up to three agents to simultaneously arbitrate for the
system bus with one to two symmetric agents (on BREQ[1:0]#) and one priority agent (on
BPRI#). P6 family processors arbitrate as symmetric agents. The priority agent normally
arbitrates on behalf of the I/O subsystem (I/O agents) and memory subsystem (memory
agents). Owning the bus is a necessary condition for initiating a bus transaction.
3-3