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ELECTRICAL SPECIFICATIONS
Table 7-9. System Bus AC Specifications (Clock)
T#
Parameter
System Bus Frequency
T1:
BCLK Period
T1B:
BCLK to Core Logic Offset
T2:
BCLK Period Stability
T3:
BCLK High Time
T4:
BCLK Low Time
T5:
BCLK Rise Time
T6:
BCLK Fall Time
NOTES:
1.
All AC timings for the GTL+ signals are referenced to the BCLK rising edge at 0.70V at the processor
edge fingers. This reference is to account for trace length and capacitance on the processor substrate,
allowing the processor core to receive the signal with a reference at 1.25V. All GTL+ signal timings are
referenced at 1.00V at the processor edge fingers.
2.
All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.70V at the processor
edge fingers. This reference is to account for trace length and capacitance on the processor substrate,
allowing the processor core to reference voltage of 1.25V. All CMOS signal timings are referenced at
1.25V at the processor edge fingers.
3.
The internal core clock frequency is derived from the system bus clock. The system bus clock to core
clock ratio is determined during initialization as described in Section 7.5. Table 7-10 shows the supported
ratios for each processor.
4.
The BCLK period allows a +0.5 ns tolerance for clock driver variation.
5.
The BCLK offset time is the absolute difference needed between the BCLK signal rising edge arriving at
the S.E.C. cartridge edge finger at 0.7V vs. arriving at the core logic at 1.25V. The positive offset is
needed to account for the delay between the Slot 1 connector and processor core. The positive offset
ensures both the processor core and the core logic receive the BCLK edge concurrently.
See Chapter 9, System Bus Signal Simulations for system bus clock signal quality specifications.
6.
7.
Due to the difficulty of accurately measuring processor clock jitter in a system, it is recommended that a
clock driver be used that is designed to meet the period stability specification into a test load of 10 to
20 pF on the rising edges of adjacent BCLKs crossing 1.25V at the pin of the processor core. The jitter
present must be accounted for as a component of BCLK timing skew between devices.
8.
The clock driver's closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The –20 dB attenuation point of the clock driver, as measured into a 10
to 20 pF load, should be less than 500 kHz. This specification may be ensured by design characterization
and/or measured with a spectrum analyzer.
9.
Not 100% tested. Specified by design/characterization as a clock driver requirement.
7-20
Min
Nom
Max
66.67
15.0
0.78
±300
4.70
5.10
0.75
1.95
0.75
1.95
(1, 2)
Unit
Figure
MHz
All processor core
frequencies
ns
7-6
3, 4
ns
7-7
Absolute Value
ps
7, 8
ns
7-6
@>1.7V
ns
7-6
@<0.7V
ns
7-6
0.7V–1.8V
ns
7-6
1.8V–0.7V
Notes
(3)
(5, 6)
(9)
(9)
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