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COMPONENT INTRODUCTION
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Processor Core
®
Pentium
Pro Processor
Dual Die Cavity Package
Figure 1-1. Second Level Cache Implementations
The S.E.C. cartridge has the following features: a thermal plate, a cover and a substrate with
an edge finger connection. The thermal plate allows standardized heatsink attachment or
customized thermal solutions. The full enclosure also protects the surface mount components.
The edge finger connection maintains socketability for system configuration. The edge finger
connector is notated as 'Slot 1 connector' in this and other documentation.
1.2.
TERMINOLOGY
In this document, a '#' symbol after a signal name refers to an active low signal. This means
that a signal is in the active state (based on the name of the signal) when driven to a low
level. For example, when FLUSH# is low, a flush has been requested. When NMI is high, a
non-maskable interrupt has occurred. In the case of signals where the name does not imply an
active state but describes part of a binary sequence (such as address or data), the '#' symbol
implies that the signal is inverted. For example, D[3:0] = 'HLHL' refers to a hex 'A', and
D#[3:0] = 'LHLH' also refers to a hex 'A' (H= High logic level, L= Low logic level).
The term "system bus" refers to the interface between the processor, system core logic (a.k.a.
the core logic components) and other bus agents. The system bus is a multiprocessing
interface to processors, memory and I/O. The term "cache bus" refers to the interface
between the processor and the L2 cache components (TagRAM and BSRAMs). The cache
bus does NOT connect to the system bus, and is not visible to other agents on the system bus.
When signal values are referenced in tables, a 0 indicates inactive and a 1 indicates active. 0
and 1 do not reflect voltage levels. A # after a signal name indicates active low. An entry of
1 for ADS# means that ADS# is active, with a low voltage level.
1-2
L2
Processor
Core
Tag
Schematic only
Pentium II Processor
Substrate and Components
L2
000756c
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