The P6 family and the Pentium II processor system bus incorporate several advanced data
integrity features to improve error detection, retry, and correction. The Pentium II processor
system bus includes parity protection for address/request signals, parity or protocol protection
on most control signals, and ECC protection for data signals. The P6 family provides the
maximum possible level of error detection by incorporating functional redundancy checking
(FRC) support.
The P6 family data integrity features can be categorized as follows:
•
Processor internal error detection
•
Level 2 (L2) cache and Core-to-L2 cache-interface error detection and limited recovery
•
®
Pentium
II processor system bus error detection and limited recovery
•
Pentium II processor system bus FRC support
In addition, the P6 family extends the Pentium II processor's data integrity features in several
ways to form a machine check architecture. Several model specific registers are defined for
reporting error status. Hardware corrected errors are reported to registers associated with the
unit reporting the error. Unrecoverable errors cause the INT 18 machine check exception, as
in the Pentium Pro processor.
If machine check is disabled, or an error occurs in a Pentium II processor system bus agent
without the machine check architecture, the Pentium II processor system bus defines a bus
error reporting mechanism. The central agent can then be configured to invoke the exception
handler via an interrupt (NMI) or soft reset (INIT#).
The terminology used in this chapter is listed below:
•
Machine Check Architecture (MCA)
•
Machine Check Exception (MCE)
•
Machine Check Enable bit (CR4.MCE)
•
Machine Check In Progress (MCIP)
For more information on Machine Check Architecture, see the Intel Architecture Software
Developer's Manual, Volume 3: System Programming Guide.
4.1.
ERROR CLASSIFICATION
The Pentium II processor system bus architecture uses the following error classification. An
implementation may always choose to report an error in a more severe category to simplify
its logic.
CHAPTER 4
DATA INTEGRITY
4-1