Intel Pentium II Developer's Manual page 120

GTL+ INTERFACE SPECIFICATIONS
The maximum acceptable Flight Time is determined on a net-by-net basis, and is usually
different for each unique driver-receiver pair. The maximum acceptable Flight Time can be
calculated using the following equation (known as the setup time equation):
T
FLIGHT_MAX
Where:
T is the maximum clock-to-out delay of a driving agent,
CO-MAX
T is the minimum setup time required by a receiver on the same net,
SU-MIN
T
CLK_SKEW-MAX
the receiver's clock inputs, and
T
CLK_JITTER-MAX
CLK is the host clock adjustment factor.
ADJ
T - an empirical timing adjustment factor that accounts for timing "pushout" seen
ADJ
when multiple bits change state at the same time. The factors that contribute to the
adjustment factor include crosstalk on the PCB, substrate, and packages,
simultaneous switching noise, and edge rate degradation caused by inductance in the
ground return path.
The above equation should be checked for all pairs of devices on all nets of a bus.
The minimum acceptable Flight Time is determined by the following equation (known as the
hold time equation):
T
= T + CLK
FLIGHT_MIN HOLD
Where:
T —the minimum clock to output specification.
CO-MIN
T —the minimum flight time.
FLT-MIN
T —the minimum specified input hold time.
HOLD
CLK —the maximum variation between components receiving the same clock edge.
SKEW
CLK —the host clock adjustment factor.
ADJ
The Hold time equation is independent of clock jitter, since data is released by the driver and
is required to be held at the receiver on the same clock edge.
8-12
= Clock Period - T
- T
CLK_JITTER-MAX
is the maximum anticipated time difference between the driver's and
is maximum anticipated edge-to-edge phase jitter.
+ CLK - T
SKEW ADJ
- T - T
CO-MAX SU-MIN
- CLK - T
ADJ ADJ
CO_MIN
CLK_SKEW-MAX