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MICRO-ARCHITECTURE OVERVIEW
System
Memory
L2 Cache
There are two types of memory access: loads and stores. Loads only need to specify the
memory address to be accessed, the width of the data being retrieved, and the destination
register. Loads are encoded into a single µop.
Stores need to provide a memory address, a data width, and the data to be written. Stores
therefore require two µops, one to generate the address and one to generate the data. These
µops must later re-combine for the store to complete.
Stores are never performed speculatively since there is no transparent way to undo them.
Stores are also never re-ordered among themselves. A store is dispatched only when both the
address and the data are available and there are no older stores awaiting dispatch.
A study of the importance of memory access reordering concluded:
•
Stores must be constrained from passing other stores, for only a small impact on
performance.
•
Stores can be constrained from passing loads, for an inconsequential performance loss.
•
Constraining loads from passing other loads or stores has a significant impact on
performance.
The Memory Order Buffer (MOB) allows loads to pass other loads and stores by acting like a
reservation station and re-order buffer. It holds suspended loads and stores and re-dispatches
them when a blocking condition (dependency or resource) disappears.
2-8
Memory
I/F
Figure 2-7. Inside the Bus Interface Unit
Memory
Order Buffer
DCache
From Address
Generation Unit
To/From
Instruction Pool
(ReOrder Buffer)
000930
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