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ELECTRICAL SPECIFICATIONS
Table 7-15. System Bus AC Specifications (TAP Connection)
T#
Parameter
T30:
TCK Frequency
T31:
TCK Period
T32:
TCK High Time
T33:
TCK Low Time
T34:
TCK Rise Time
T35:
TCK Fall Time
T36:
TRST# Pulse Width
T37:
TDI, TMS Setup Time
T38:
TDI, TMS Hold Time
T39:
TDO Valid Delay
T40:
TDO Float Delay
T41:
Non-Test Outputs Valid
Delay
T42:
Non-Test Inputs Setup Time
T43:
Non-Test Inputs Setup Time
T44;
Non-Test Inputs Hold Time
NOTES:
1.
All AC timings for the TAP signals are referenced to the TCK rising edge at 0.70V at the processor edge
fingers. All TAP signal timings are referenced at 1.25V at the processor edge fingers.
2.
Not 100% tested. Guaranteed by design characterization.
3.
1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
4.
Referenced to TCK rising edge.
5.
Referenced to TCK falling edge.
6.
Valid delay timing for this signal is specified to 2.5V +5%. See Table 7-3 for pull-up resistor values.
7.
Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO and
TMS). These timings correspond to the response of these signals due to TAP operations.
8.
During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
9.
These values are not tested during manufacturing.
7-24
Min
Max
Unit
16.667
MHz
60.0
ns
25.0
ns
25.0
ns
5.0
ns
5.0
ns
40.0
ns
5.5
ns
14.5
ns
2.0
13.5
ns
28.5
ns
2.0
27.5
ns
27.5
ns
5.5
ns
14.5
ns
(1)
Figure
Notes
7-6
7-6
@1.7V
(2)
7-6
@0.7V
(2)
7-6
(0.7V–1.7V)
(2, 3)
7-6
(1.7V–0.7V)
(2, 3)
(2)
7-13
Asynchronous
7-12
4
7-12
4
7-12
5, 6
7-12
2, 5, 6
7-12
5, 7, 8
7-12
2, 5, 7, 8
7-12
4, 7, 8
7-12
4, 7, 8
, 9
, 9
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