Intel Pentium II Developer's Manual page 5

7.2.1. Normal State - State 1....................................................................................... 7-3
7.2.2. Auto HALT Power Down State - State 2............................................................. 7-3
7.2.3. Stop-Grant State - State 3 ................................................................................. 7-3
7.2.4. HALT/Grant Snoop State - State 4..................................................................... 7-4
7.2.5. Sleep State - State 5 ......................................................................................... 7-4
7.2.6. Deep Sleep State - 6 ......................................................................................... 7-5
7.2.7. Clock Control and Low Power Modes................................................................... 7-5
7.3. POWER AND GROUND PINS................................................................................. 7-5
7.4. DECOUPLING GUIDELINES................................................................................... 7-6
Pentium ® II Processor Vcc CORE Decoupling ...................................................... 7-6
7.4.1.
7.4.2. System Bus GTL+ Decoupling ............................................................................. 7-6
7.5. SYSTEM BUS CLOCK AND PROCESSOR CLOCKING .......................................... 7-7
7.5.1. Mixing Processors of Different Frequencies ......................................................... 7-9
7.6. VOLTAGE IDENTIFICATION................................................................................... 7-9
PENTIUM ® II PROCESSOR SYSTEM BUS UNUSED PINS ...................................7-11
7.7.
PENTIUM ® II PROCESSOR SYSTEM BUS SIGNAL GROUPS..............................7-12
7.8.
7.8.1. Asynchronous vs. Synchronous for System Bus Signals .....................................7-12
7.9. TEST ACCESS PORT (TAP) CONNECTION..........................................................7-14
7.10. MAXIMUM RATINGS .............................................................................................7-14
7.11. PROCESSOR SYSTEM BUS DC SPECIFICATIONS..............................................7-14
PENTIUM ® II PROCESSOR SYSTEM BUS AC SPECIFICATIONS ........................7-19
7.12.
CHAPTER 8
GTL+ INTERFACE SPECIFICATIONS
8.1. SYSTEM SPECIFICATION...................................................................................... 8-1
8.1.1. System Bus Specifications................................................................................... 8-2
8.1.2. System AC Parameters: Signal Quality ................................................................ 8-3
8.1.2.1. RINGBACK TOLERANCE ................................................................................ 8-5
8.1.3. AC Parameters: Flight Time................................................................................. 8-7
8.2. GENERAL GTL+ I/O BUFFER SPECIFICATION ....................................................8-13
8.2.1. I/O Buffer DC Specification .................................................................................8-13
8.2.2. I/O Buffer AC Specifications................................................................................8-14
8.2.3. Determining Clock-to-Out, Setup and Hold..........................................................8-14
8.2.3.1. CLOCK-TO-OUTPUT TIME, T CO ...................................................................8-14
8.2.3.2. MINIMUM SETUP AND HOLD TIMES ............................................................8-16
8.2.3.3. RECEIVER RINGBACK TOLERANCE ............................................................8-19
8.2.4. System-Based Calculation of Required Input and Output Timings .......................8-19
8.2.4.1. CALCULATING TARGET T FLIGHT_MAX .......................................................8-19
8.2.4.2. CALCULATING TARGET T HOLD ...................................................................8-20
8.3. PACKAGE SPECIFICATION ..................................................................................8-20
CHAPTER 9
SIGNAL QUALITY SPECIFICATIONS
9.1. SYSTEM BUS CLOCK (BCLK) SIGNAL QUALITY SPECIFICATIONS ..................... 9-1
9.2. GTL+ SIGNAL QUALITY SPECIFICATIONS............................................................ 9-3
9.3. NON-GTL+ SIGNAL QUALITY SPECIFICATIONS................................................... 9-3
9.3.1. Overshoot/Undershoot Guidelines ....................................................................... 9-3
9.3.2. Ringback Specification......................................................................................... 9-4
9.3.3. Settling Limit Guideline ........................................................................................ 9-5
CONTENTS
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