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GTL+ INTERFACE SPECIFICATIONS
8.2.2.
I/O Buffer AC Specifications
Table 8-4 contains the I/O Buffer AC parameters.
Symbol
dV/dt
Output Signal Edge Rate, rise
EDGE
dV/dt
Output Signal Edge Rate, fall
EDGE
NOTES:
1.
This is the maximum instantaneous dV/dt over the entire transition range (Hi-to-Lo or Lo-to-Hi) as
measured at the driver's output pin while driving the Ref8N network, with the driver and its package
model located near the center of the network.
2.
These are design targets. The acceptance of the buffer is also based on the resultant signal quality. In
addition to edge rate, the shape of the rising edge can also have a significant effect on the buffer's
performance, therefore the driver must also meet the signal quality criteria in the next section. For
example, a rising linear ramp of at 0.8V/ns will generally produce worse signal quality (more ringback)
than an edge that rolls off as it approaches V
to-Lo edge rates may exceed this specification and produce acceptable results with a corresponding
reduction in V
. For instance, a buffer with a falling edge rate larger than 1.5V/ns can been deemed
OL
acceptable because it produced a V
and maximum edge rate specifications.
3.
The minimum edge rate is a design target, and slower edge rates can be acceptable, although there is a
timing impact associated with them in the form of an increase in flight time, since the signal at the receiver
will no longer meet the required conditions for T
more details on the effects of edge rates slower than 0.3V/ns.
8.2.3.
Determining Clock-to-Out, Setup and Hold
This section describes how to determine setup, hold and clock to out timings.
8.2.3.1.
CLOCK-TO-OUTPUT TIME, T
T
is measured using the test load in Figure 8-9, and is the delay from the 1.5V crossing
CO
point of the clock signal at the clock input pin of the device, to the V
the output signal at the output pin of the device. For simulation purposes, the test load can be
replaced by its electrical equivalent, which is a single 50Ω resistor connected directly to the
package pin and terminated to 1.5V.
In a production test environment, it is nearly impossible to measure T
output pin of the device, instead, the test is performed a finite distance away from the pin and
compensated for the finite distance. The test load circuit shown in Figure 8-9 takes this into
account by making this finite distance a 50Ω transmission line. To get the exact timings at
the output pin, the propagation delay along the transmission line must be subtracted from the
measured value at the probe point.
T
measurement for a Lo-to-Hi signal transition is shown in Figure 8-10. The T
CO
measurement for Hi-to-Lo transitions is similar.
8-14
Table 8-4. I/O Buffer AC Parameters
Parameter
even though it might have exceeded that rate earlier. Hi-
TT
less than 500 mV. Lo-to-Hi edges must meet both signal quality
OL
SU
Min
Max
Units
0.3
0.8
V/ns
0.3
0.8
V/ns
. Refer to Section 8.1.3. on computing flight time for
CO
Figure
Notes
1, 2, 3
1, 2, 3
crossing point of
REF
directly at the
CO
CO
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