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MICRO-ARCHITECTURE OVERVIEW
•
The RETIRE unit: An in-order unit that knows how and when to commit ("retire") the
temporary, speculative results to permanent architectural state.
•
The BUS INTERFACE unit: A partially ordered unit responsible for connecting the
three internal units to the real world. The bus interface unit communicates directly with
the L2 (second level) cache supporting up to four concurrent cache accesses. The bus
interface unit also controls a transaction bus, with MESI snooping protocol, to system
memory.
2.2.1.
The Fetch/Decode Unit
Figure 2-4 shows a more detailed view of the Fetch/Decode unit.
ICache
Instruction
Decoder
(x3)
The L1 Instruction Cache is a local instruction cache. The Next_IP unit provides the L1
Instruction Cache index, based on inputs from the Branch Target Buffer (BTB), trap/interrupt
status, and branch-misprediction indications from the integer execution section.
The L1 Instruction Cache fetches the cache line corresponding to the index from the
Next_IP, and the next line, and presents 16 aligned bytes to the decoder. The prefetched
bytes are rotated so that they are justified for the instruction decoders (ID). The beginning
and end of the Intel Architecture instructions are marked.
Three parallel decoders accept this stream of marked bytes, and proceed to find and decode
the Intel Architecture instructions contained therein. The decoder converts the Intel
Architecture instructions into triadic µops (two logical sources, one logical destination per
2-4
From Bus Interface Unit
Next_IP
Branch Target
Buffer
Microcode
Instruction
Sequencer
Register Alias
Table Allocate
Figure 2-4. Inside the Fetch/Decode Unit
To Instruction
Pool (ReOrder Buffer)
000927
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