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GTL+ INTERFACE SPECIFICATIONS
V
start
V
+0.2
REF
V
REF
V
–0.2
REF
Figure 8-12. Standard Input Hi-to-Lo Waveform for Characterizing Receiver Setup Time
The recommended procedure for extracting T
additional steps, it would be beneficial that any such extra steps be documented with the
results of this receiver characterization:
The full receiver circuit must be used, comprising the input differential amplifier, any
shaping logic gates, and the edge-triggered (or pulse-triggered) flip-flop. The output of
the flip-flop must be monitored.
The receiver's Lo-to-Hi hold time should be determined using a nominal input waveform that
starts at V
IN_LOW_MAX
with the process, temperature, voltage, and V
fastest (or best) corner values (yielding the longest T
(system) reference voltage at the device pin. Due to tolerance in V
the voltage divider generating system V
by a maximum of ±122 mV. When determining hold time, the internal reference voltage
V
(at the reference gate of the diff. amp.) must be set to the value which
REF_INTERNAL
yields the worst case hold time. Here, V
Where, V
is the net maximum differential noise amplitude on the component's
NOISE
internal V
distribution bus (at the amplifier's reference input gate) comprising noise
REF
picked up by the connection from the V
Analogously, for the hold time of Hi-to-Lo transitions, the input starts at V
V
+200 mV and drops to < 0.5 V at the rate of 3V/ns.
REF
8-18
Time
HOLD
(V
–200 mV) and goes to V
REF
from V
REF
REF_INTERNAL
package pin to the input of the amp.
REF
1.5V Clk Ref
Clock
T
SU
is outlined below. If one employs
, at a fast edge rate of 0.8V/ns,
TT
of the receiver set to the
REF_INTERNAL
). Here, V
HOLD
TT
(±2%), V
can shift around 1V
TT
REF
= V
±(122 mV +V
REF
000958
is the external
REF
(1.5V, ±9%) and
).
NOISE
=
IN_HIGH_MIN
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