Sd Card Interface - Xilinx KC705 User Manual

Evaluation board for the kintex-7 fpga

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User manual (118 pages)

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Table Of Contents

Table of Contents

Chapter 1: KC705 Evaluation Board Features

Four data lines and the FPGA CCLK pin are wired to the Quad-SPI Flash memory. A

common chip select (FPGA_FCS) shared between the Linear BPI Flash and the Quad-SPI

Flash is controlled by the configuration mode settings on DIP switch SW13 position 5 (M0)

and a one-of-two demultiplexer device U64. If mode pin M0 = 1, the SPI device is selected.

If mode pin M0 = 0, the Linear BPI Flash device is selected. The connections between the

SPI Flash memory and the FPGA are listed in

Table 1-6: Quad-SPI Flash Memory Connections to the FPGA

Notes:

1. FPGA_FCS connected to FPGA U1 pin U19 becomes QSPI_IC_CS_B through U64 and J3.

The configuration section of UG470, 7 Series FPGAs Configuration User Guide provides

details on using the Quad-SPI Flash memory.

Quad-SPI Flash memory on the KC705 board.

For more information about the Numonyx N25Q128A13BSF40F see

X-Ref Target - Figure 1-6

VCC2V5

R20

R19

DNP

4.7kΩ 5%

FLASH_D3

R429

15Ω 1%

QSPI_IC_CS_B

R430

15Ω 1%

FLASH_D1