Sd Card Interface - Xilinx KC705 User Manual

SD Card Interface

[Figure
The KC705 board includes a secure digital input/output (SDIO) interface to provide
user-logic access to general purpose nonvolatile SDIO memory cards and peripherals. The
SD card slot is designed to support 50 MHz high speed SD cards.
The SDIO signals are connected to I/O bank 12 which has its VCCO set to VADJ. A Texas
Instruments I TXB0108 8-bit bidirectional voltage-level translator is used between the
FPGA and the SD card connector (U9).
interface on the KC705 board.
X-Ref Target - Figure 1-7
SDIO_DAT0_LS
SDIO_DAT1_LS
SDIO_DAT2_LS
To FPGA
Bank 12 SDIO_CD_DAT3_LS
(U1)
SDIO_CMD_LS
SDIO_CLK_LS
Table 1-7
Table 1-7: SDIO Connections to the FPGA
U1 FPGA Pin Schematic Net Name
Y21 SDIO_SDWP
AA21 SDIO_SDDET
AB22 SDIO_CMD_LS
AB23 SDIO_CLK_LS
AA22 SDIO_DAT2_LS
AA23 SDIO_DAT1_LS
KC705 Evaluation Board
UG810 (v1.6.2) August 26, 2015
1-2, callout 5]
VADJ
51.1K 1% Six Places
0.1μF 25V
X5R
U57
TXB0108
Voltage-Level
Translator
VCCB
VCCA
A1
A2
A3
A4
A5
A6
NC
A7
NC
A8
OE
C543
0.1μF 25V
X5R
GND
Figure 1-7: SD Card Interface
lists the SD card interface connections to the FPGA.
I/O Standard
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
LVCMOS25
www.xilinx.com
Figure 1-7 shows the connections of the SD card
VCC3V3 VCC3V3
51.1K 1% Six Places
C22
GND
B1
B2
B3
SDIO_CD_DAT3
B4
B5
B6
SDIO_SDDET
B7 To FPGA
Bank 12
B8
(U1)
GND
GND
VADJ
U57 Level Shifter
Pin Name (A) Pin Name (B)
N/A N/A
N/A N/A
A5 B6
A6 B7
A3 B4
A2 B3
Feature Descriptions
VCC3V3
C22
0.1μF 25V
X5R
GND
U9
SDIO Card
Connector
4
VDD
7
SDIO_DAT0
DAT0
8
SDIO_DAT1
DAT1
9
SDIO_DAT2
DAT2
1
CD_DAT3
2
SDIO_CMD
CMD
5
SDIO_CLK
CLK
10
DETECT
IOGND2
11
SDIO_SDWP
PROTECT
IOGND1
12
NC
D_P
GNDTAB4
GNDTAB3
3
VSS1 GNDTAB2
6
VSS2 GNDTAB1
GND
UG810_c1_07_031214
U9 SDIO Connector
Pin Number Pin Name
11
10
2
5
9
8
Send Feedback
18
17
16
15
14
13
GND
SDWP
SDDET
CMD
CLK
DAT2
DAT1
23