Revision History - Xilinx ZC702 User Manual

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Revision History

The following table shows the revision history for this document.
Date Version
05/24/2012 1.0
10/08/2012 1.1
ZC702 Board User Guide
UG850 (v1.3) June 4, 2014
Initial Xilinx release.
The board photo in Figure 1-2
Option Settings was added. The part number in
changed to N25Q128A13ESF40F. In
Device mode. The frequency jitter in
to 50 ppm. The action description under
The 34 differential user-defined signals are defined as 34 LA pairs, LA00–LA33, in
LPC Connectors J3 and J4, page
pairs changed to 68 single-ended or 34 differential user-defined signals.
Appendix F, Regulatory and Compliance Information
Declaration of Conformity and markings for waste electrical and electronic
equipment (WEEE), restriction of hazardous substances (RoHS), and CE compliance.
www.xilinx.com
Revision
was updated. Table 1-2, Switch SW16 Configuration
Quad-SPI Flash Memory, page 20
Table 1-6, the J35 shunt controls OTG and
System Clock, page 28
Program_B Pushbutton, page 49
51. In the same section, 34 differential user-defined
now includes a link to the
changed from 20 ppm
changed.
2