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5.2 Control Registers
The interrupt control registers are comprised of the processor status word (PSW), interrupt vector register, non-
maskable control register, group interrupt control register, interrupt accepted group register and external interrupt
condition specification register.
5.2.1
Registers List
Table: 5.2.1 shows the interrupt control registers.
Table:5.2.1 Interrupt Control Register List
Register
CPU register
PSW
Interrupt vector
IVAR0
register
IVAR1
IVAR2
IVAR3
IVAR4
IVAR5
IVAR6
Non-maskable
G0ICR
interrupt›
(NMICR)
Address
R/W
Access size
-
R/W
16
0x00008000
R/W
16
0x00008004
R/W
16
0x00008008
R/W
16
0x0000800C
R/W
16
0x00008010
R/W
16
0x00008014
R/W
16
0x00008018
R/W
16
0x00008900
R/W
8,16
Functions
Processor status word
Interrupt vector register 0
Interrupt vector register 1
Interrupt vector register 2
Interrupt vector register 3
Interrupt vector register 4
Interrupt vector register 5
Interrupt vector register 6
Non-maskable interrupt control regis-
ter
Chapter 5
Interrupt Controller
Page
V-9
V-10
V-10
V-11
V-11
V-11
V-11
V-11
V-12
Control Registers
V - 7
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