Interrupt Controller Setup - Panasonic MN103S User Manual

Chapter 5
Interrupt Controller
Interrupt Acceptance Timing
If an interrupt request occurs part-way through the execution of an instruction, even instructions which require
multiple execution cycles such as multiply/divide and other instructions are aborted if possible and the interrupt is
accepted. The aborted instruction is executed again after returning from interrupt processing. Aborting these
instructions sets the interrupt acceptance prohibited interval to 11 cycles or less.(The maximum interrupt prohib-
ited interval of 11 cycles occurs when saving or restoring all registers with the MOVM, CALL, or RET instruc-
tions. This occurs only for special cases such as task context switching.)
Stack Frame
When an interrupt is accepted, a stack flame is allocated and the total 6 bytes of information in the PC and PSW
are saved in order to return form the interrupt. However, since transferring data across the 32-bit boundary is pro-
hibited, the SP value must constantly be set to a multiple of 4. Accordingly, a stack flame is allocated as shown in
Figure: 5.3.3 so that the SP value is constantly set to a multiple of 4. Ultimately, an 8-byte area with a total of 6
bytes of information is saved.
5.3.3

Interrupt Controller Setup

Interrupt Flag Setup Procedure
The following shows the setup procedure of the interrupt flag including the software change of the interrupt
request flag.
(1) Disable all maskable interrupts.
PSW
bp11: IE = 0
(2) Select the interrupt factor
(3) Clear the interrupt request flag and the
interrupt detection flag.
GnICR
IR of the interrupt factor = 0
ID of the interrupt factor = 1
(4) Set the interrupt level
GnICR
bp14-12: GnLV2-0
(5) Enable the interrupt.
GnICR
IE of the interrupt factor = 1
V - 38 Interrupt Controller Operation
+3
Smaller address
(Rsv.)
PC (Return address)
Figure:5.3.3 Stack Flame Configuration
Setup Procedure
+2 +1 4n
SP (After the interrupt)
PSW
SP (Before the interrupt)
(1) Clear the IE flag of the PSW to "0" to disable all
maskable interrupts.
(2) Select the interrupt factor such as timer interrupt cycle
change.
(3) Change the IR flag corresponding to the interrupt factor
of the group n interrupt control register (GnICR) to "0"
and the ID flag to "1" simultaneously. By changing
these flags simultaneously, the IR flag of the request
flag and the ID flag of the detection flag are cleared to
"0".
(4) Set the interrupt level by the GnLV2-0 flag of the GnICR
register.
(5) Set the IE flag corresponding to the interrupt factor of the
GnICR to "1" to enable the interrupt.
Description