Panasonic MN103S User Manual page 251

Timer 8 Compare/Capture A Register (TM8CA: 0x0000A208) [16-bit Access Register]
bp 15 14
Flag TM TM
CA15 CA14
At reset 0 0
Access R/W R/W
This is a register which has compare operation and capture operation. For the appropriate use of both operations,
this register is set by the TMAM1-0 flag of the timer compare capture A(B) register. For compare operation,
select the compare capture register to be used as double buffer or single buffer. For capture operation, set the both-
edge or one-edge of an input pin to the capture timing.
1. When the compare/capture register is set to compare operation
The interrupt request (TMAIRQ, TMBIRQ) is generated at the time when the binary counter (TMnBC) and
the compare capture register (TMnCA, TMnCB) match. Figure: 9.2.1 shows the block diagram of the compare
capture/register.
Timer compare/capture A and B register
Capture timing
Timing of load to
compare register
When the compare capture register is set to the double buffer, the value of the TMnCA (TMnCB) is retained in
the compare register buffer once; so, when the it is read again after writing to the TMnCA (TMnCB), the pre-
vious value may be returned. Table: 9.2.3 shows the timing when the compare/capture register is updated at
double buffer.
13 12 11 10
TM TM TM TM
CA13 CA12 CA11 CA10
0 0 0 0
R/W R/W R/W R/W
Compare/capture register
Compare register buffer
Register write
Data bus
Figure:9.2.1 Block Diagram of Compare/Capture Register
9 8 7 6
TM TM TM TM
CA9 CA8 CA7 CA6
0 0 0 0
R/W R/W R/W R/W
TMnBC
binary counter
Match interrupt request
Compare/capture A(B) register
TMnCA (TMnCB)
5 4 3 2
TM TM TM TM
CA5 CA4 CA3 CA2
0 0 0 0
R/W R/W R/W R/W
Register read
Control registers
Chapter 9
16-bit Timer
1 0
TM TM
CA1 CA0
0 0
R/W R/W
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