Rom Correction Data Registers - Panasonic MN103S User Manual

6.2.4

ROM Correction Data Registers

Each of these registers specifies the correction data (channel number) used for ROM correction. Data can be writ-
ten only when the RCRWE flag in the ROM correction control register (RCRCTR) is "1".
ROM Correction 0 Data Register (RCR0DR: 0x7FF00108) [32-bit access register]
bp 63 62
Flag RC0 RC0
DT63 DT62
At reset x x
Access R/W R/W
bp 47 46
Flag RC0 RC0
DT47 DT46
At reset x x
Access R/W R/W
bp 31 30
Flag RC0 RC0
DT31 DT30
At reset x x
Access R/W R/W
bp 15 14
Flag RC0 RC0
DT15 DT14
At reset x x
Access R/W R/W
bp Flag Description
RC0DT63 ROM correction 0 correction data
63-56 to
RC0DT56
RC0DT55 ROM correction 0 correction data
55-48 to
RC0DT48
RC0DT47 ROM correction 0 correction data
47-40 to
RC0DT40
RC0DT39 ROM correction 0 correction data
39-32 to
RC0DT32
RC0DT31 ROM correction 0 correction data
31-24 to
RC0DT24
RC0DT23 ROM correction 0 correction data
23-16 to
RC0DT16
RC0DT15 ROM correction 0 correction data
15-8 to
RC0DT8
RC0DT7 ROM correction 0 correction data
7-0 to
RC0DT0
61 60 59 58
RC0 RC0 RC0 RC0
DT61 DT60 DT59 DT58
x x x x
R/W R/W R/W R/W
45 44 43 42
RC0 RC0 RC0 RC0
DT45 DT44 DT43 DT42
x x x x
R/W R/W R/W R/W
29 28 27 26
RC0 RC0 RC0 RC0
DT29 DT28 DT27 DT26
x x x x
R/W R/W R/W R/W
13 12 11 10
RC0 RC0 RC0 RC0
DT13 DT12 DT11 DT10
x x x x
R/W R/W R/W R/W
57 56 55 54
RC0 RC0 RC0 RC0
DT57 DT56 DT55 DT54
x x x x
R/W R/W R/W R/W
41 40 39 38
RC0 RC0 RC0 RC0
DT41 DT40 DT39 DT38
x x x x
R/W R/W R/W R/W
25 24 23 22
RC0 RC0 RC0 RC0
DT25 DT24 DT23 DT22
x x x x
R/W R/W R/W R/W
9 8 7 6
RC0 RC0 RC0 RC0
DT9 DT8 DT7 DT6
x x x x
R/W R/W R/W R/W
Set condition
Data of the address (lower 3bits set to 7) to be corrected
Data of the address (lower 3bits set to 6) to be corrected
Data of the address (lower 3bits set to 5) to be corrected
Data of the address (lower 3bits set to 4) to be corrected
Data of the address (lower 3bits set to 3) to be corrected
Data of the address (lower 3bits set to 2) to be corrected
Data of the address (lower 3bits set to 1) to be corrected
Data of the address (lower 3bits set to 0) to be corrected
53 52 51 50
RC0 RC0 RC0 RC0
DT53 DT52 DT51 DT50
x x x x
R/W R/W R/W R/W
37 36 35 34
RC0 RC0 RC0 RC0
DT37 DT36 DT35 DT34
x x x x
R/W R/W R/W R/W
21 20 19 18
RC0 RC0 RC0 RC0
DT21 DT20 DT19 DT18
x x x x
R/W R/W R/W R/W
5 4 3 2
RC0 RC0 RC0 RC0
DT5 DT4 DT3 DT2
x x x x
R/W R/W R/W R/W
ROM Correction Control Registers
Chapter 6
ROM Correction
49 48
RC0 RC0
DT49 DT48
x x
R/W R/W
33 32
RC0 RC0
DT33 DT32
x x
R/W R/W
17 16
RC0 RC0
DT17 DT16
x x
R/W R/W
1 0
RC0 RC0
DT1 DT0
x x
R/W R/W
VI - 7