Panasonic MN103S User Manual page 548

Page Section
9-25 Upper
table
9-38 Table
Setup
Proce-
dure (2)
Descrip-
tion(2)
9-41 Table
Setup
Proce-
dure (3)
Descrip-
tion(3)
9-55 Table
Setup
Proce-
dure (2)
Descrip-
tion(2)
9-61 Line 3 to
6
Figure
9.8.3
Table
Setup
Proce-
dure (2)
Descrip-
tion(2)
9-64 Figure
9.9.1
Record of Changes - 11
Definition Previous Edition (Ver.1)
Change 15 14
TMXF -
0 0
R/W R
Change Set the compare/capture register
TM8CA(0x0000A208)=0x09C3
⋅⋅⋅ The setting is 2499 (0x09C3) due to
Change
2500 counts.
Change Set the interrupt generation cycle
TM8CA(0x0000A208)=0x4E1F
⋅⋅⋅ The setting is 19999 (0x4E1F) due to
Change
20000 counts.
Change Set the interrupt generation cycle
TM8CA(0x0000A208)=0x4E1F
⋅⋅⋅ The setting is 19999 (0x4E1F) due to
Change
20000 counts.
Change The output pin (TM8AIO) using timer 8
outputs waveforms as shown below
(repeating "L" output for 2 ms and
"H" output for the next 1 ms). IOCLK is
selected as clock source to match the
binary counter and the compare/capture
A register for every 2 ms and to match
the binary counter and the compare/cap-
ture B register for every
3 ms.
Change
Output pin
(TM8AIO)
Change Set the repeating cycle
TM8CA(0x0000A208)=0x9C3F
⋅⋅⋅ The setting is 39999 (0x9C3F) due to
Change
40000 counts.
Change
Count clock
Caputure input
edge
Binary counter
Compare/capture
register
Interrupt request
flag
13 12 11
TMTGE TMONE TMCLE
0 0 0
R/W R/W R/W
2 ms
3 ms
0006 0007 0008 0000 0001 0002 0003 0000 0001 0002
0008 0003
New Edition (Ver.1.1)
15 14 13
TMXF - TMTGE TMONE TMCLE
0 0 0
R R R/W
Set the compare/capture register
TM8CA(0x0000A208)=0x0EA5
⋅⋅⋅ The setting is 3749 (0x0EA5) due to
3750 counts.
Set the interrupt generation cycle
TM8CA(0x0000A208)=0x752F
⋅⋅⋅ The setting is 29999 (0x752F) due to
30000 counts.
Set the interrupt generation cycle
TM8CA(0x0000A208)=0x752F
⋅⋅⋅ The setting is 29999 (0x752F) due to
30000 counts.
The output pin (TM8AIO) using timer 8
outputs waveforms as shown below
(repeating "L" output for 1.5 ms and
"H" output for the next 0.5 ms). IOCLK is
selected as clock source to match the
binary counter and the compare/capture
B register for every 1.5 ms and to match
the binary counter and the compare/cap-
ture A register for every
2 ms.
Output pin
(TM8BIO)
1.5ms
2ms
Set the repeating cycle
TM8CB(0x0000A20C)=0xAFC7
⋅⋅⋅ The setting is 44999 (0xAFC7) due to
45000 counts.
Count clock
Caputure input
edge
Edge detection
flag
Binary counter
006 007 008 009 010 000 001
Compare/capture
register
Interrupt request
flag
12 11
0 1
R/W R/W
002 003 004 000 001 002
010 004