Setup Example - Panasonic MN103S User Manual

8.7.2

Setup Example

Cascade Connection Setup Example
Setting example of timer function that an interrupt is constantly generated by cascade connection of timer 0 and
timer 1, as a 16-bit timer is shown. An interrupt is generated 30000 times every 1 ms by selecting clock source
IOCLK. Oscillation frequency is set to 10 MHz, 6 multiplication and IOCLK=MCLK/2.
An example setup procedure, with a description of each step is shown below.
Setup Procedure
(1) Stop the counter
TM1MD(0x0000A181)
bp6: TM0LDE=0
bp7: TM0CNE=0
TM0MD(0x0000A180)
bp6: TM0LDE=0
bp7: TM0CNE=0
(2) Disable the interrupt
G3ICR(0x0000890C)
bp8: G3IE0=0
bp9: G3IE1=0
(3) Set the interrupt generation cycle
TM1BR(0x0000A189)=0x75
TM0BR(0x0000A188)=0x2F
(4) Select the count clock source
TM1MD(0x0000A181)
bp2-0: TM1CK2-0=011
TM0MD(0x0000A180)
bp2-0: TM0CK2-0=000
(5) Initialize the timer 0 and 1
TM1MD(0x0000A181)
bp6: TM1LDE=1
TM0MD(0x0000A180)
bp6: TM0LDE=1
(6) Set the interrupt level
G3ICR(0x0000890C)
bp14-12: G3LV2-0=100
(7) Enable the interrupt
G3ICR(0x0000890C)
bp9: G3IE1=1
(1) Set the TM1LDE flag and the TM1CNE flag of the timer
1 mode register (TM1MD) to "0" to stop the counter. Set
the TM0LDE flag and TM0CNE flag of the timer 0 mode
register (TM0MD) to "0" to stop the timer 1 counting.
(2) Set the G3IEO flag of the G3ICR register to "0" to
disable the timer 0 underflow interrupt. Set the G3IE1
flag of the G3ICR register to "0" to disable the timer 1
underflow interrupt.
(3) Set the interrupt generation cycle to the timer 0 base
register (TM0BR) and timer 1 base register (TM1BR). It
is set to 29999 (0x752F) due to 30000 dividing.
(4) Select the count clock source (cascading with the timer
0) by the TM1CK2-0 flag of the TM1MD register. Select
the count clock source (IOCLK) by the TM0CK2-0 flag
of the TM0MD register.
(5) Set the TM1LDE flag of the TM1MD register to "1" to
initialize the timer 1. Set the TM0LDE flag of the
TM0MD register to "1" to initialize the timer 0. The
value of the TM1BR register is loaded into the TM1BC
counter; and, the value of the TM0BR register is loaded
into the TM0BC counter. Reset the TM1LDE flag and
the TM0LDE flag to "0" after the setting.
(6) Set the interrupt level by the G3LV2-0 flag of the G3ICR
register. If any interrupt request flag may be already
set, clear all request flags.
(7) Set the G3IE1 flag of the G3ICR register to "1" to enable
the interrupt. Leave the G3IE0 as it is "0" with interrupts
disabled.
Description
Cascade Connection
Chapter 8
8-bit Timer
VIII - 45