Panasonic MN103S User Manual page 335

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Setting PWM Output Timing
PWM output timing can be shifted by the PWM output timing control register (PWMDCNT) within PWM period.
Set the SETENn flag of the PWMMDn register to "1" to valid shift function of PWM output timing.
The relationship between the register value and PWM output timing is shown below.
When the SDIRn flag is set to "0", PWM output timing shifts and to "1", it shifts back.
When PWM output timing shifts beyond PWM period, the exceeding period comes out in the opposite side of the
shift direction in the same period. (when shifting back, it comes out forward and when shifting ahead, it comes out
backward).
In using saw-tooth wave, PWM output timing can shift only ahead.
Period setting
TCM PnA
TCM PnB
TCM PnC
PWMn0
NPWMn0
PWMn1
NPWMn1
PWMn2
NPWMn2
PWMn0
NPWMn0
PWMn1
NPWMn1
PWMn2
NPWMn2
PWMn0
NPWMn0
PWMn1
NPWMn1
PWMn2
NPWMn2
SDIR n= 0
STIMn7- 0 = 0x00
0x30
SDIRn= 1
STIMn7- 0 = 0x30
Figure:10.3.7 PWM Output Timing Control
SDIRn=1
STIMn7-0=0x80
Figure:10.3.8 Output Timing at exceeding PWM period
Perod setting
TCM PnA
TCM PnB
TCM PnC
PWMn0
NPWMn0
PWMn1
NPWMn1
PWMn2
NPWMn2
0x20
PWMn0
NPWMn0
PWMn1
NPWMn1
PWMn2
NPWMn2
Chapter 10
Motor Control PWM
SDIRn= 0
STIMn7- 0 = 0x00
SDIRn= 0
STIMn7- 0 = 0x20
Operation
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