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11.1.2
Block Diagram
Watchdog Timer Block Diagram
Internal reset signal
SYSCLK
Oscillation
stabilization
wait release
interrupt
WD0VFIRQ
Hard reset signal
Internal reset
generation
Binary counter
Reset
8-bit binary counter
WDBC
Reset
Control register
Clock source
WDCTR
selection
Interrupt counter
Figure:11.1.1 Watchdog Timer Block Diagram
8
1/2
10
1/2
12
1/2
14
1/2
16
1/2
16-bit binary counter
Watchdog Timer
RSTCTR register
NRST
Reset
OSCI
Overview
Chapter 11
XI - 3
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