Control Registers; Clock Generator Control Register; Pll Control Registers - Panasonic MN103S User Manual

3.2 Control Registers

3.2.1

Clock Generator Control Register

Table:3.2.1 shows the internal clock supply.
Table:3.2.1 Clock Generator Control Register
Clock generator
R/W Readable / Writable
R Readable
W Writable
3.2.2

PLL Control Registers

PLL Control Register (PCNT: 0x0000AFF2) [8, 16-bit Access Register]
bp 15 14
Flag - -
At reset 0 0
Access R R
bp Flag Description
15-6 - -
5 PLLSEL Select the PLL output
4 - -
3 PLLON Set the PLL ON/OFF
2 - -
CKSEL1 Select the PLL multiplication ratio of
1-0
CKSEL0 oscillation frequency
Register Address
PCNT 0x0000AFF2
CKCTR 0x00008280
13 12 11 10
- - - -
0 0 0 0
R R R R
R/W Access size
R/W 8, 16
R/W 8, 16
9 8 7 6
- - - -
0 0 0 0
R R R R
Set condition
-
0: Oscillation clock (OSCI)
1: PLL output
-
0: PLL ON
1: PLL OFF
-
00: 4 multiplication of oscillation frequency
01: 6 multiplication of oscillation frequency
10: 8 multiplication of oscillation frequency
11: Setting prohibited
When changing the PLLON flag and the CKSEL[1:0] flag of the
PCNT register, the PLLSEL flag must be set to "0".
And then, set the PLLSEL flag to "1" after waiting for more than
200 µs
Description
PLL control register
Clock control register
5 4 3 2
PLL PLL
-
-
SEL ON
0 0 0 0
R/W R R/W R
Control Registers
Chapter 3
Clock Generator
Page
III-3
III-5
1 0
CK CK
SEL1 SEL0
0 0
R/W R/W
III - 3