Pin Functions - Panasonic MN103S User Manual

Chapter 1
Overview
1.3.3

Pin Functions

Table:1.3.2 Pin Functions
TQFP 48
Name
Pin No.
VDD 12
VDD 32
VDD 54
VDD 76
VDD2 33
VDD2 80
VSS 10
VSS 29
VSS 56
VSS 78
VDD3 31
VPPEX 30
OSC1 28
OSC0 27
NRST 39
P10 34
P11 35
P12 36
P13 37
P14 38
P16 40
P17 41
P20 42
P21 43
P22 44
P23 45
P24 46
P25 47
P26 48
P27 49
I - 12 Pin Description
I/O Other Function
- -
- -
- -
- -
-
input -
output
input -
I/O IRQ04
IRQ05
IRQ06
IRQ07
IRQ08
TM7IO
SBO2
I/O SBT2
SBI2
SBO1
SBT1
SBI1
SBO0
SBT0
SBI0
Function
Power supply pin Power pins for 5 V, digital IO
Apply 5 V to all of pins and connect capacitor
of over 10 µF between all of the VDD and
VSS pins.
It is recommended that total capacitance
between all of the VDD and VSS is more than
10-times sum of capacitance between all of
the VDD2 and VSS plus capacitance etween
VDD3 and VSS.
Power supply pin Power pins for 1.8 V, digital IO
Connect capacitor of over 1 mF between all
of the VDD2 and VSS pins. .
Power supply pin GND for digital
Power supply pin Power pin for 3.3 V, flash
Connect capacitor of over 2 µF between
VDD3 and VSS pins.
N, C for mask ROM version
Power supply pin Power for flash EEPROM
Connect with VDD3.
N, C for mask ROM version
Clock input pin Extend ceramic or crystal oscillators or input
Clock output pin a clock to OSC1.
Reset pins This pin resets the chip when power is turned
(negative logic) on and contains an internal pull-up resistor.
Setting this pin "L" level initializes the internal
state of the device. Thereafter, setting the
input to "H" level releases the reset. The
hardware waits for the system clock to
stabilize, and processes the reset interrupt.
Connect capacitor of over 0.1 µF between
NRST and VSS pins.
I/O port 1 8-bit CMOS I/O ports.
Each bit can be set individually as either
input or output by the P1DIR register.
Pull-up resistor for each bit can be selected
individually by the P1PLU register.
At reset, the input mode (P10 to P14, P16,
P17) is selected, and pull-up resistor is
disabled.
I/O port 2 8-bit CMOS I/O ports.
Each bit can be set individually as either
input or output by the P2DIR register.
Pull-up resistor for each bit can be selected
individually by the P2PLU register.
At reset, the input mode (P20 to P27) is
selected, and pull-up resistor is disabled.
Description