Panasonic MN103S User Manual page 539

Page Section Definition
II-19 Table Change
2.6.2
II-20 Table Change
2.6.2
III-3 PLL Change
control
register
III-7 Figure Change
3.3.1
Table Change
3.3.4
IV-5 Internal Change
ROM
Access
Control
Resister
Note Add
V-8 Accepted Change
group
V-21 bp Change
10,9,6,5
Previous Edition (Ver.1.1)
Address F E D C B A
x'0000800X IVAR3
x'0000801X
x'0000804X
x'0000807X
x'0000820X
x'0000828X
x'0000890X G3ICR
x'0000891X G7ICR
x'0000892X G11ICR
x'0000A45X AN1BUF05 AN1BUF04
AN1BUF09 AN1BUF08
x'0000A46X
x'0000A47X
x'0000A48X
AN2CTREGA
AN2BUF09 AN2BUF08
x'0000A49X
x'0000A4AX AN2BUF13 AN2BUF12
x'0000A4BX Reserved Reserved
AN2BUF01 AN2BUF00
x'0000A4CX
x'0000A51X Reserved
Reserved
x'0000AFFX Reserved Reserved
x'7FF0000X
RCR0DR
x'7FF0010X
bp ... Set condition
1-0 ... 11: Setting prohibited
on
OSCI
R
x
R
d
Frequency ... Recommended circuit constant
It is described after matching evaluation.
bp ... Set condition
9-8 ... 01: 2 cycle(2xMCLK) access
10: 3 cycle(2xMCLK) access
-
Resister Address R/W ...
IAGR 0x00008A00 R/W ...
G11IE2 Timer12 compare/capture B interrupt
enable flag
G11IE1 Timer12 compare/capture A interrupt
enable flag
G11IR2 Timer12 compare/capture B interrupt
request flag
G11IR1 Timer12 compare/capture A interrupt
request flag
Address
9 8 7 6 5 4 3
x'0000800X
IVAR2 IVAR1
x'0000801X
IVAR6 IVAR5
x'0000804X
x'0000807X
ROMCTR
x'0000820X
RSTCTR
x'0000828X
x'0000890X
G2ICR
x'0000891X
G6ICR G5ICR
x'0000892X
G10ICR G9ICR
x'0000A45X
AN1BUF03
AN1BUF07 x'0000A46X
x'0000A47X
Reserved
x'0000A48X
ADST2 AN2CTR1
AN2BUF07 x'0000A49X
x'0000A4AX
AN2BUF11
AN2BUF15 x'0000A4BX
Reserved x'0000A4CX
x'0000A51X
Reserved
x'0000AFFX
Reserved PCN
x'7FF0000X
x'7FF0010X
bp
1-0
on
Internal
feedback
resistor
R =1 MΩ
F
(typ)
Frequency ...
[Hz]
5.000M
l
15.000M
bp
9-8
When the CPU clock ... is not guranteed.
Resister
IAGR
G11IE2 Timer12 compare B interrupt enable flag
G11IE1 Timer12 compare A interrupt enable flag
G11IR2 Timer12 compare B interrupt request flag
G11IR1 Timer12 compare A interrupt request flag
New Edition (Ver.1.2)
F E D C B A 9 8 7
IVAR3 IVAR2
IVAR6
ROMCTR
G3ICR G2ICR
G7ICR G6ICR
G11ICR G10ICR
AN1BUF05 AN1BUF04
AN1BUF09 AN1BUF08
ADST2
AN2CTREGA
AN2BUF09 AN2BUF08
AN2BUF13 AN2BUF12
Reserved Reserved
Reserved Reserved
Reserved
Reserved
Reserved Reserved
RCR0DR
... Set condition
... 11: Setting prohibited
When changing the PLLON
flag... more than 200ms.
OSCI
R
x
R
d
Recommended circuit constant
... Load Capacity ... Dumping resistor
... (47) ...
... (15) ...
... Set condition
... 01: 2 cycle(2xMCLK) access
If CPU clock ..., it is prohibited.
10: 3 cycle(2xMCLK) access
When the CPU clock ..., is
switched from "0" to "1".
Address R/W ...
0x00008A00 R ...
Record of Changes - 2
6 5 4 3
IVAR1
IVAR5
RSTCTR
Reserved
G5ICR
G9ICR
AN1BUF03
AN1BUF07
Reserved
AN2CTR1
AN2BUF07
AN2BUF11
AN2BUF15
Reserved
Reserved
Reserved PCN
Internal
feedback
resistor
R =1 MΩ
FB
(typ)
0
0