Panasonic MN103S User Manual page 257

Timer 9 Mode Register (TM9MD: 0x0000A220) [8, 16-bit Access Register]
bp 15 14
Flag TM -
XF
At reset 0 0
Access R R
bp Flag Description
Timer operation display
15 TMXF
14 - -
Timer external trigger enable
13 TMTGE
Timer 1-shot operation enable
12 TMONE
Timer binary counter enable
11 TMCLE
Timer count control input enable
10 TMCGE
Up/down counting selection
TMUD1
9-8
TMUD0
Timer operation enable
7 TMCNE
Timer initialization
6 TMLDE
5-3 - -
Timer count clock source selection
TMCK2
2-0 TMCK1
TMCK0
13 12 11 10
TM TM TM TM
TGE ONE CLE CGE
0 0 1 0
R/W R/W R/W R/W
9 8 7 6
TM TM TM TM
UD1 UD0 CNE LDE
0 0 0 0
R/W R/W R/W R/W
Setting condition
0: Timer stopped
1: Timer operating
-
0: Timer activation disabled by external trigger. (trigger input ignored)
1: Timer start when the falling edge is input
(when timer A pin polarity selection bit is "0")
Timer start when the rising edge is input
(when timer A pin polarity selection bit is "1")
0: 1-shot operation disabled (timer does not stop)
1: 1-shot operation enabled (timer stops when TMBC and TMCA match)
0: Clear operation disabled
1: Clear operation enabled
When the TMCA is set to a compare register
TMBC is cleared when the TMBC and the TMCA match.
When the TMCA is set to a capture register
TMBC is cleared when captured to TMCA.
0: Count control disabled by the TMAIN pin input
1: Refer to the following table.
TMAIN pin input
"L"
"H"
00: Up counting
01: Down counting
10: Up counting (when "H" level is input to the TMAIN pin)
Down counting (when "L" level is input the TMAIN pin)
11: Up counting (when "L" level is input the TMAIN pin)
Down counting (when "H" level is input to the TMAIN pin)
When the 2-phase encoding (1-fold, 4-fold) is selected as the count clock
source, set "00".
0: Operation disabled
1: Operation enabled
0: Normal operation
1: Initialization
TMBC=0x0000
When the TMCA and TMCB are set to the compare register of the double
buffer, the value is loaded into the compare register from the buffer. Pin out-
put is initialized.
-
000: IOCLK
001: IOCLK/8
010: IOCLK/64
011: Timer 3 underflow
100: 2-phase encoding (1-fold)
101: 2-phase encoding (4-fold)
110: TMBIN pin input (both edges)
111: TMBIN pin input (single edge)
When pin input (single edge) is selected by the timer, the edge selected by
the B pin polarity selection bit of the TMMDB register is counted.
When using IOCLK/8 and IOCLK/64, operation must be enabled respec-
tively by the prescaler control registers (TMPSCNE) and (TMEXPSC16).
5 4 3 2
- - - TM
CK2
0 0 0 0
R R R R/W
Timer A pin polarity selection bit
"0"
Stop counting
Counting Stop counting
Control registers
Chapter 9
16-bit Timer
1 0
TM TM
CK1 CK0
0 0
R/W R/W
"1"
Counting
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