Panasonic MN103S User Manual page 142

Chapter 6
ROM Correction
ROM Correction 2 Address Register (RCR2AR: 0x7FF00120) [32-bit access register]
bp 31
Flag RC2
CEN
At reset 0
Access R/W
bp 15
Flag RC2
AD15
At rest x
Access R/W
bp Flag
31 RC2CEN
30-20 -
RC2AD19
19-0 to
RC2AD0
ROM Correction 3 Address Register (RCR3AR: 0x7FF00130) [32-bit access register]
bp 31
Flag RC3
CEN
At reset 0
Access R/W
bp 15
Flag RC3
AD15
At reset x
Access R/W
bp Flag
31 RC3CEN
30-20 -
RC3AD19
19-0 to
RC3AD0
VI - 6 ROM Correction Control Registers
30 29 28 27
- - - -
0 0 0 0
R R R R
14 13 12 11
RC2 RC2 RC2 RC2
AD14 AD13 AD12 AD11
x x x x
R/W R/W R/W R/W
Description
ROM correction channel 2 enabled
-
ROM correction channel 2 address
30 29 28 27
- - - -
0 0 0 0
R R R R
14 13 12 11
RC3 RC3 RC3 RC3
AD14 AD13 AD12 AD11
x x x x
R/W R/W R/W R/W
Description
ROM correction channel 3 enable
-
ROM correction channel 3 address
26 25 24 23
- - - -
0 0 0 0
R R R R
10 9 8 7
RC2 RC2 RC2 RC2
AD10 AD9 AD8 AD7
x x x x
R/W R/W R/W R/W
Set condition
0: ROM correction disabled
1: ROM correction enabled
-
These bits specify the lower 20 bits of the ROM address subject to
ROM correction. 8 bytes of data from the above ROM address to
(ROM address + 7) are subject to ROM correction.
26 25 24 23
- - - -
0 0 0 0
R R R R
10 9 8 7
RC3 RC3 RC3 RC3
AD10 AD9 AD8 AD7
x x x x
R/W R/W R/W R/W
Set condition
0: ROM correction disabled
1: ROM correction enabled
-
These bits specify the lower 20 bits of the ROM address subject to
ROM correction. 8 bytes of data from the above ROM address to
(ROM address + 7) are subject to ROM correction.
22 21 20 19
- - - RC2
AD19
0 0 0 x
R R R R/W
6 5 4 3
RC2 RC2 RC2 RC2
AD6 AD5 AD4 AD3
x x x x
R/W R/W R/W R/W
22 21 20 19
- - - RC3
AD19
0 0 0 x
R R R R/W
6 5 4 3
RC3 RC3 RC3 RC3
AD6 AD5 AD4 AD3
x x x x
R/W R/W R/W R/W
18 17 16
RC2 RC2 RC2
AD18 AD17 AD16
x x x
R/W R/W R/W
2 1 0
RC2 RC2 RC2
AD2 AD1 AD0
x x x
R/W R/W R/W
18 17 16
RC3 RC3 RC3
AD18 AD17 AD16
x x x
R/W R/W R/W
2 1 0
RC3 RC3 RC3
AD2 AD1 AD0
x x x
R/W R/W R/W