Chapter 3 Clock Generator - Panasonic MN103S User Manual

Chapter 2
CPU Basics
Table:2.2.1 Block Diagram and Function
Blocks
Clock generator
Program counter
Instruction queue
Instruction decoder
Instruction
execution controller
Extension function
AU
LU
Barrel shifter
IInternal ROM, RAM
Address register
Data register
Interrupt control
Bus control
Internal peripheral functions
II - 4 Block Diagram
Description
Uses a clock oscillator circuit driven by an external crystal or ceramic resonator to supply clock signals
to CPU blocks.
Generates addresses for the instructions to be inserted into the instruction queue. Normally
incremented by sequencer indication, but may be set to branch destination address or ALU operation
result when branch instructions or interrupts occur.
Stores the instructions up to execution.
Decodes the instruction queue, sequentially generates the control signals needed for instruction
execution, and executes the instruction by controlling the blocks within the chip.
Controls CPU block operations in response to the result decoded by the instruction decoder and
interrupt requests.
Executes extended instructions such as high-speed multiplication and multiply and accumulate opera-
tion instructions.
Executes arithmetic operations.
Executes logic operations.
Executes shift operations.
Assigned to the execution program, data and stack region.
Be used as address pointers and supports the operation instructions (addition, subtraction, and com-
parison) involved in address calculations.
Can use generally for all operations.
Detects interrupt requests from peripheral functions, requests CPU shift to interrupt processing.
Controls connection of CPU internal bus and CPU external bus. Includes bus usage arbitration
function.
Includes peripheral functions (A/D converter, 3-phase PWM, serial I/F, 8-bit timer, 16-bit timer).
Peripheral functions vary depending on the model.