Panasonic MN103S User Manual page 125

Figure: 5.3.1 shows the interrupt sequence flow. (when not accepting multiple interrupts) The numbers in the fig-
ure correspond to the steps in the previous list.
Interrupt
max. 11 Cycles
Figure:5.3.1 Interrupt Sequence (Interrupt Sequence by the Interrupt Handler)
Speed-up of the Interrupt Handler Processing
An even higher interrupt response speed can be realized by assigning only one factor to a single interrupt level.
Figure: 5.3.2 shows the interrupt sequence flow when assigning one factor to a single interrupt level.
Figure:5.3.2 Speed-up of the Interrupt Handler Processing
Multiple Interrupts
When a level interrupt occurs, multiple interrupts are disabled by clearing IE of the PSW. However, multiple
interrupts can be achieved even while processing level interrupts by setting IE to "1" during processing. However,
in order for multiple interrupts to occur, the interrupts must have a higher priority than interrupt musk level IM2 to
IM0 of the PSW at that time. (The GnICR interrupt level LV2 to LV0 is smaller than the PSW interrupt mask level
IM2 to IM0.) When non-maskable interrupts occur, multiple interrupts of level interrupts and non-maskable inter-
rupts are disabled until the non-maskable interrupt processing program is finished by the execution of the RTI
instruction.
Program
Processing for each level
1
2
5
6
Program
Interrupt
max. 11 Cycles
Handler (pre-processing)
Processing for each group
Processing for
3
each factor
4
Interrupt
processing
program
Handler (post processing)
Processing for each factor
1
Handler (pre-processing)
Interrupt
processing
program
5
6
Handler (post-processing)
Interrupt Controller Operation
Interrupt Controller
Interrupt processing
and interrupt request
cancel
Chapter 5
V - 37