Panasonic MN103S User Manual page 33

TQFP 48
Name I/O
Pin No.
P31 50 I/O
P32 51
P33 52
P34 53
P35 55
P36 57
P37 58
P42 59 I/O
P43 60
P46 61
P47 62
P51 63 I/O
P52 64
P53 65
P54 66
P55 67
P56 68
P57 69
P62 70 I/O
P63 71
P64 72
P65 73
P66 74
P67 75
P72 77 I/O
P73 79
P80 1 I/O
P81 2
P82 3
P83 4
P90 6 I/O
P91 7
P92 8
P93 9
P94 11
P95 13
P96 14
P97 15
PA0 16 I/O
PA1 17
PA2 18
PA3 19
PA4 20
PA5 21
PA6 22
PA7 23
Other Function
TM1IO
TM2IO
TM3IO
TM4IO
TM5IO
TM8AIO
TM8BIO
TM9AIO
TM9BIO
TM10AIO
TM10BIO
TM7IO
PWM00
NPWM00
PWM01
NPWM01
PWM02
NPWM02
PWM10
NPWM10
PWM11
NPWM11
PWM12
NPWM12
TM11IO0
TM11IO1
IRQ00
IRQ01
IRQ02
IRQ03
ADIN00
ADIN01
ADIN02
ADIN03
ADIN04
ADIN05
ADIN06
ADIN07
ADIN08
ADIN09
ADIN10
ADIN11
ADIN12
ADIN13
ADIN14
ADIN15
Function
I/O port 3 8-bit CMOS I/O ports.
Each bit can be set individually as either
input or output by the P3DIR register.
Pull-up resistor for ech bit can be selected
individually by the P3PLU register.
At reset, the input mode (P31 to P37) is
selected, and pull-up resistor is disabled.
I/O port 4 8-bit CMOS I/O port.
Each bit can be set individually as either
input or output by the P4DIR register.
Pull-up resistor for each bit can be selected
individually by the P4PLU register.
At reset, the input mode (P42, P43, P46,
P47) is selected and pull-up resistor is dis-
abled.
I/O port 5 8-bit CMOS I/O ports.
Each bit can be set individually as either
input or output by the P5DIR register.
Pull-up resistor for each bit can be selected
individually by the P5PLU register.
At reset, the input mode (P51 to P57) is
selected, and pull-up resistor is disabled.
I/O port 6 8-bit CMOS I/O ports.
Each bit can be set individually as either
input or output by the P6DIR register.
Pull-up resistor for each bit can be selected
individually by the P6PLU register.
At reset, the input mode (P62 to P67) is
selected, and pull-up resistor is disabled.
I/O port 7 8-bit CMOS I/O ports.
Each bit can be set individually as either
input or output by the P7DIR register.
P pull-up resistor for each bit can be selected
individually by the P7PLU register.
At reset, the input mode (P72, P73) is
selected, and pull-up resistor is disabled.
8-bit CMOS input ports.
I/O port 8
Each bit can be set individually as either
input or output by the P8PLU register.
Pull-up resistor for each bit can be selected
individually by the P8PLU register.
At reset, the input mode (P80 to P83) is
selected, and pull-up resistor is disabled.
I/O port 9 8-bit CMOS input ports.
Each bit can be set individually as either
input or output by the P9DIR register.
Pull-up resistor for each bit can be selected
individually by the P9PLU register.
At reset, the input mode (P90 to P97) is
selected, and pull-up resistor is disabled.
I/O port A 8-bit CMOS input ports.
Each bit can be set individually as either
input or output by the PADIR register.
Pull-up resistor for each bit can be selected
individually by the PAPLU register.
At reset, the input mode (PA0 to PA7) is
selected, and pull-up resistor is disabled.
Chapter 1
Overview
Description
Pin Description I - 13