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Count Timing of PWM Output (1)
The polarity for output pins changes by matching of the binary counter and the compare/capture A register and
matching of the binary counter and the compare/capture B register. Table 9.8.4 shows the preconditions for PWM
output count timing, and Figure; 9.8.1 shows count timing.
Table:9.8.4 Preconditions of Count TIming of PWM Output
Operation condition
TImer up/down selection
TImer compare/capture operation mode selection
Timer output waveform selection
Timer pin polarity selection
Timer counter clear enable
Count
clock
TMnCNE
flag
Compare/capture B
register
Compare/capture A
register
Binary counter
Output pin
(TMnAEG=0)
Output pin
(TMnAEG=1)
Setting description
Up counting
Compare register (single buffer)
Set when TMnBC and TMnCB match
Reset when TMnBC and TMnCA match
Positive polarity output (TMnAEG=0)
Negative polarity output (TMnAEG=1)
Clear operation enabled
0000 0001
M-1
M M+1 M+2
Setup time for compare/capture B register
Setup time for compare/capture A register
Figure:9.8.1 Count Timing of PWM Output (1)
M
N
N-1
N 0000 0001
Chapter 9
16-bit Timer
M-1
M
PWM Output
IX - 59
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