Chapter 16
Appendix
16.4 Extension Instruction Specification
16.4.1
Arithmetic extension function
Arithmetic Extension Function
The block diagram is shown below in which extension arithmetic units are connected to this series CPU core.
With the MN103S00 Series, multipliers capable of 32 × 32 multiply operation, multiply and accumulate
arithmetic units capable of 32 × 32 + 64 multiply and accumulate operation, priority encoders and saturation
compensation arithmetic units are incorporated as standard. Extension instructions using such extension
arithmetic units are described in this section.
Instruction data Instruction address
XVI - 38
Extension Instruction Specification
Instruction
decoding section
Instruction
queue
Program
counter
Register
section
Operand data
Figure:16.4.1 Block Diagram of the Extension Arithmetic Units
Microcontroller
core instruction
decoder
Barrel
shifter
LU
AU
Operand address
Arithmetic
Arithmetic
extension
extension
section A
section B
Extension
Extension
instruction
instruction
decoder B
decoder A
Extension
Extension
arithmetic
arithmetic
unit A
unit B
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