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Clock
pin
(SBT2
)
Input pin
pin
(SBO2
)
Transfer bit
counter
SC2RBSY
Interrupt
(SC2TIRQ)
Figure:13.3.11 Reception Timing (Falling Edge, With Start Condition)
At master
Tmax=3.5T
Clock
pin
(SBT2
)
Input pin
(SBO2
pin
)
Transfer bit
counter
SC2RBSY
(Data set to SC2TB)
Interrupt
(SC2TIRQ)
Figure:13.3.12 Reception Timing (Falling Edge, Without Start Condition)
T
T
0
1
2
T
0
1
2
3
4
5
6
3
4
5
Serial Interface 2
7
6
7
Operation
Chapter 13
XIII - 21
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