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Chapter 9
16-bit Timer
Count Timing of Event Count Operation
TMnBIN pin input is sampled by IOCLK. The edge selected by the TMnBIN pin input is counted, and the binary
counter counts up. The pulse width should be IOCLK × 1.5 or more for detecting the edge. Table: 9.5.4 shows
operation condition and Figure: 9.5.1 the count timing.
Table:9.5.4 Operation Condition
Operation condition
Input edge
Timer up/down selection
Timer compare/capture A operation mode selection
Timer counter clear enable
IOCLK
Pin input
(TMnBIN)
TMLDE
flag
TMCNE
flag
Compare/capture
register
Binary counter
Interrupt
request flag
Setting the Count Control Input
The count clock of the binary counter can masked based on the input level of the TMnMAIN pin. The timer count
control input is enabled by setting the TMCGE flag of the timer mode register (TMnMD) to "1". The input level
for masking is set by the TMAEG flag of the timer compare/capture A mode register (TMnMDA). Table: 9.5.5
shows the relationship between the input level and TMAEG flag.
Table:9.5.5 Input Level and TMAEG flag
TMnAIN pin
"H"
"L"
IX - 44
Event Count
Setting description
Rising edge
Up counting
Compare register (single buffer)
Clear operation enabled
Sampling
0000
Figure:9.5.1 Count Timing of Event Count Operation
TMAEG flag (TMnMDA register)
0
Normal operation
(counting)
Count clock masked
(stop counting)
Sampling
N
0001
N-1
Count clock masked
(stop counting)
Normal operation
Sampling
N
0000
1
(counting)
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