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Chapter 2
CPU Basics
2.1 Overview
Table: 2.1.1 shows basic specifications.
Table:2.1.1 Basic Specifications
Structure
Instructions
Basic performance
Pipeline
Address space
II - 2
Overview
Load/store architecture
(9 registers)
Load/store architecture
(Others)
Number of instructions
Addressing modes
Basic instruction length
Code assignment
Maximum Internal operating frequency
Minimum instruction execution cycle
Inter-register operations
Load/store
Conditional branch
5-stage (instruction fetch, decode, execution, memory access, write-back)
4 GB
Data: 32-bit x 4
Address: 32-bit x 4
Stack pointer: 32-bit x 1
PC: 32-bit × 1
PSW : 16-bit × 1
Multiply/divide register: 32-bit x 1
Branch target register: 32-bit x 2
46
6
1 byte
1 byte to 2 bytes (basic part) + 0 byte to 6
bytes (extension)
60.0 MHz (External oscillation 10MHz)
1 clock (16.7 nsec)
1 clock
1 clock
1 clock to 3 clock
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