Panasonic MN103S User Manual page 234

Chapter 8
8-bit Timer
Selecting the Count Source
Select any desired count source for the lowest-order timer. Set the count clock source for high-order timers (
except the lowest-order timer) to "cascading".
For example, when using timers 0 and 1 as a 16-bit timer, set a desired count clock source for timer 0 and the
count clock source for timer 1 to "cascading". When using timers 1, 2 and 3 as a 32-bit timer , set a desired count
clock source for timer 0 and the count clock source for timer 1 to "cascading".
Setting the Timer Base Register
Set a timer division ratio in timer base register (TMnBR).
Timer interrupt cycle = (TMnBR setting + 1) × Count clock source cycle
For example, when using timers 0 and 1 as a 16-bit timer and setting the interrupt cycle to "0x2000",
"0x1FFF(0x2000-1)" should be set the TMnBR register. Set "0x1F" to the upper TM1BR register and "0xFF" to
the lower TM0BR register. It is possible to set the TMnBR register by 16-bit access simultaneously when using
timer 1 + timer 0, timer 3 + timer 2, timer 5 + timer 4, timer 7 + timer 6, timer 15 + timer 14 or timer 17 + timer
16 as a 16-bit timer. (Not when timer 2 + timer 1, timer 6 + timer 5 and timer 16 + timer 15 are cascaded as a 24-
bit timer or 32-bit timer.)
Initializing the timer
Set the TMnLDE flags of all cascaded timers to "1" to initialize the timers. (It is not necessary to set all registers
at the same time.)
Enabling Counting Operation
When enabling timer counting operation, enable the counting operation of the cascaded timers in sequence start-
ing from the highest-order timer, or enable the counting operation for all of the cascaded timers simultaneously.
Stopping Counting Operation
When stopping timer counting operation, stop the counting operation of the cascaded timers in sequence starting
from the lowest-order timer, or stop the counting operation for all of the cascaded timers simultaneously.
Timer Outputs
The timer output from the highest of the cascaded timers can be used. Operation of the timer output from the
lower cascaded timers is not guaranteed.
Interrupt Requests
The interrupt requests from the highest of the cascaded timers can be used. The interrupt requests from the lower
cascaded timers are not generated, but set timers to interrupts disabled.
Changing the Time Base Register during Counting Operation
When timer 1 + timer 0, timer 3 + timer 2, timer 5 + timer 4, timer 7 + timer 6 , timer 15 + timer 14, or timer 17
+ timer 16 are used as a 16-bit timer, the TMnBR register during counting operation can be changed via 16-bit
access.When using other combination as a 16-bit timer or 32-bit timer, avoid load timing to the binary counter.
Combined 8-bit access registers can be used with 16-bit access at cascade connection.
(when the addresses of the registers are consecutive)
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VIII - 44 Cascade Connection