Panasonic MN103S User Manual page 442

Chapter 14
A/D Converter
(4) Set the AD0: Set the AN0CTR0 register
Set the operation mode
AN0CTR0(0x0000A400)
bp1-0: AN0MD1-0=01
Set the conversion clock
AN0CTR0(0x0000A400)
bp4-2: AN0CK2-0=011
Set the conversion start channel
AN0CTR0(0x0000A400)
bp10-8: AN0CH2-0=000
Set the conversion complete channel
AN0CTR1(0x0000A404)
bp14-12: AN0NCH2-0=010
Set the power-down mode
AN0CTR0(0x0000A400)
bp6: AN0OFF=1
(5) Set the AD0: Select the AD0 start trigger
ADST0(0x0000A408)
bp2-0: AD0ST2-0=010
(6) Set the external trigger conversion start
enabled
AN0CTR0(0x0000A400)
bp5: AN0TRG=1
(7) Set the AD0: Set the interrupt level
G26ICR(0x00008968)
bp14-12: G26LV2-0=100
(8) Set the AD0: Enable the interrupt
G26ICR(0x00008968)
bp8: G26IE0=1
(9) Set the timer 12: Select the cycle
TM12CA(0x0000A288)=0x752F
(10) Set the timer 12: Set the count clock source
TM12MD(0x0000A280)
bp2-0: TMCK2-0=000
(11) Set the timer 12: Select up/down
TM12MD(0x0000A280)
bp9-8: TMUD1-0=00
(12) Set the timer 12: Set the counter clear
enabled
TM12MD(0x0000A280)
bp11: TMCLE=1
XIV - 36 Operation
Setup Procedure
(4) Set the AN0MD1-0 flags of the AN0CTR0 register to "01"
to set "multiple channels/one-timer conversion" to
operation mode.
Set the AN0CK2-0 flags of the AN0CTR0 register to
"011" to set the conversion clock to4 dividing of IOCLK.
Set the AN0CH2-0 flags of the AN0CTR0 register to
"000" to set "channel 0" to the conversion channel.
Set the AN0NCH2-0 flags of the AN0CTR0 register to
"010" to set "channel 2) to the last channel to be
converted.
Set the AN0OFF flag of the AN0CTR0 register to "1" to
set operation mode to the power-down mode flag.
*After shifted to operation mode, more than 100nsec
wait time is necessary until A/D conversion start.
(5) Set the AD0ST2-0 flags of the A/D start selection
register (ADST0) to "010" to start the A/D conversion by
the timer 12 compare A interrupt.
(6) Set the AN0TRG flag of the AN0CTR0 register to "1" to
set conversion start by the timer 11 compare A
interrupt.
(7) Set the AD0 complete interrupt level by the G26LV2-0
flags of the G26ICR register. When the interrupt
request flag is already set, clear the request flag.
(8) Set the G26IE0 flag of the G26ICR register to "1" to
enable the AD0 complete interrupt.
(9) Set the cycle to the timer 12 compare/capture A register
(TM12CA). Due to 30000 dividing, the set value is
29999 (0x752F).
(10) Select the count clock source (IOCLK) by the TMCK2-0
flags of the TM12MD register.
(11) Select the timer up counting by the TMUD1-0 flags of
the TM12MD register.
(12) Set the TMCLE flag of the TM12MD register to "1" to
enable the clear operation of the TM11BC counter.
When the TM12CA register and the TM12BC counter
match, the TM12BC counter is cleared.
Description